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ECE 4371, Fall, 2014 Introduction to Telecommunication Engineering/Telecommunication Laboratory

ECE 4371, Fall, 2014 Introduction to Telecommunication Engineering/Telecommunication Laboratory. Zhu Han Department of Electrical and Computer Engineering Class 14 Oct. 20 th , 2014. Outline. Match Filter Equalizer Timing. Receiver Structure.

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ECE 4371, Fall, 2014 Introduction to Telecommunication Engineering/Telecommunication Laboratory

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  1. ECE 4371, Fall, 2014Introduction to Telecommunication Engineering/Telecommunication Laboratory Zhu Han Department of Electrical and Computer Engineering Class 14 Oct. 20th, 2014

  2. Outline • Match Filter • Equalizer • Timing

  3. Receiver Structure • Matched filter: match source impulse and maximize SNR • grx to maximize the SNR at the sampling time/output • Equalizer: remove ISI • Timing • When to sample. Eye diagram • Decision • d(i) is 0 or 1 Figure 7.20 Noisena(t) gTx(t) gRx(t) d(i) ?

  4. Matched Filter • Input signal s(t)+n(t) • Maximize the sampled SNR=s(T0)/n(T0) at time T0

  5. Matched Filter: optimal receive filter for maximized Matched filter example • Received SNR is maximized at time T0 example: transmit filter receive filter (matched)

  6. Matched Filter

  7. Matched Filter

  8. Matched Filter

  9. Matched Filter Since g(t)

  10. Properties of Matched Filters

  11. Equalizer • When the channel is not ideal, or when signaling is not Nyquist, There is ISI at the receiver side. • In time domain, equalizer removes ISR. • In frequency domain, equalizer flat the overall responses. • In practice, we equalize the channel response using an equalizer

  12. Zero-Forcing Equalizer • The overall response at the detector input must satisfy Nyquist’s criterion for no ISI: • The noise variance at the output of the equalizer is: • If the channel has spectral nulls, there may be significant noise enhancement.

  13. Transversal Transversal Zero-Forcing Equalizer • If Ts<T, we have a fractionally-spaced equalizer • For no ISI, let:

  14. Zero-Forcing Equalizer continue • Zero-forcing equalizer, figure 7.22 and example 7.3 • Example: Consider a baud-rate sampled equalizer for a system for which • Design a zero-forcing equalizer having 5 taps.

  15. MMSE Equalizer • In the ISI channel model, we need to estimate data input sequence xkfrom the output sequence yk • Minimize the mean square error.

  16. Adaptive Equalizer • Adapt to channel changes; training sequence

  17. Decision Feedback Equalizer • To use data decisions made on the basis of precursors to take care of postcursors • Consists of feedforward, feedback, and decision sections (nonlinear) • DFE outperforms the linear equalizer when the channel has severe amplitude distortion or shape out off.

  18. Different types of equalizers • Zero-forcing equalizers ignore the additive noise and may significantly amplify noise for channels with spectral nulls • Minimum-mean-square error (MMSE) equalizers minimize the mean-square error between the output of the equalizer and the transmitted symbol. They require knowledge of some auto and cross-correlation functions, which in practice can be estimated by transmitting a known signal over the channel • Adaptive equalizers are needed for channels that are time-varying • Blind equalizersare needed when no preamble/training sequence is allowed, nonlinear • Decision-feedback equalizers(DFE’s) use tentative symbol decisions to eliminate ISI, nonlinear • Ultimately, the optimum equalizer is a maximum-likelihood sequence estimator, nonlinear

  19. Timing Extraction • Received digital signal needs to be sampled at precise instants. Otherwise, the SNR reduced. The reason, eye diagram • Three general methods • Derivation from a primary or a secondary standard. GPS, atomic closk • Tower of base station • Backbone of Internet • Transmitting a separate synchronizing signal, (pilot clock, beacon) • Satellite • Self-synchronization, where the timing information is extracted from the received signal itself • Wireless • Cable, Fiber

  20. Example • Self Clocking, RZ • Contain some clocking information. PLL

  21. Timing/Synchronization Block Diagram • After equalizer, rectifier and clipper • Timing extractor to get the edge and then amplifier • Train the phase shifter which is usually PLL • Limiter gets the square wave of the signal • Pulse generator gets the impulse responses

  22. Timing Jitter • Random forms of jitter: noise, interferences, and mistuning of the clock circuits. • Pattern-dependent jitter results from clock mistuning and, amplitude-to-phase conversion in the clock circuit, and ISI, which alters the position of the peaks of the input signal according to the pattern. • Pattern-dependent jitter propagates • Jitter reduction • Anti-jitter circuits • Jitter buffers • Dejitterizer

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