1 / 6

D Ø Track trigger Liang Han and Yu-Hsiang (Louis) Lin

D Ø Track trigger Liang Han and Yu-Hsiang (Louis) Lin. Vertex & Central Tracking. 1. SMT: silicon ~ 10 m m 2. CFT: scintillating fiber ~ 100 m m. Fibers of 1 super Layer/sector:. Use look up tables of all possible combinations of ‘singlet’ or ‘doublet’ hits to define tracks in Level-1

petra
Download Presentation

D Ø Track trigger Liang Han and Yu-Hsiang (Louis) Lin

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. DØ Track triggerLiang Han and Yu-Hsiang (Louis) Lin

  2. Vertex & Central Tracking 1. SMT: silicon ~ 10 mm 2. CFT: scintillating fiber ~ 100 mm

  3. Fibers of 1 super Layer/sector:

  4. Use look up tables of all possible combinations of ‘singlet’ or ‘doublet’ hits to define tracks in Level-1 trigger

  5. PT1 effi PT1 fake FPGA Run2a 96.9% 1.0% ~50% Run2b 97.5% 0.03% ~140% • Trigger efficiency -> high • QCD fake -> low • FPGA resource -> low Good overall performance! L1CTT2b Singlet vs. current Doublet： Low fake @2E32 >10KHz! Pass DOE Review -> upgrade baseline

  6. Latest development of L1CTT2b： Aiming to reduce fake further at low PT area, we extended Singlet algorithm to the whole PT>1.5 range. preliminary studies gave positive result • we believe after pruning FPGA of all Singlet can be under control, eg • good efficiencies, eg for the hardest cut hits>100 • Fake study in progress, see Louis’ talk

More Related