Digital System Design 1

1. Digital System Design 1 Machine Organization and Hardware Programs Veton Këpuska

2. Outline of the Chapter • Start the process of developing hardware implementation of RIC. • Design will be in the form of hardware description using AHPL • Complete the details of RIC architecture. • After completing AHPL description of RIC – a simple computer, larger and more complex computer systems can be designed. Veton Këpuska

3. Basic Organization of RIC • 4 Operating Registers (Registers that Programmer has direct access to): • AC – accumulator • IX – index register • SP – stack pointer • SR – status register • 1 Non-Operating Register (Do not have instructions to load and store into PC register). • PC – Program Counter. • 3 Additional Registers not mentioned before: • IR – Instruction Register • Whenever a new instruction is fetched, it moves from memory to IR, where it is available for decoding. It is not considered Operating register since no instructions are provided to load or store data in it. • MA – Memory Address Register • During memory read/write cycle the address of memory location first loaded into MA register. • MD – Memory Data Register • Memory Read Cycle: • Address of desired Memory Word is first loaded into MA, • Word stored at that Memory location is read in MD. • Operation can be performed accessing this data. • Memory Write Cycle: • Address of desired Memory location is first loaded into MA, • Word to be stored is loaded in MD. • Word is stored at Memory location specified by MA. Veton Këpuska

4. Register Interconnection and ALU • Given the instruction set and the set of registers specification of Arithmetic Logic Unit (ALU) operations and register interconnections is required that would carry out those instructions. • Given instruction set presented earlier it can be anticipated that ALU will include: • Adder • Complementing Logic • AND, OR and XOR logic • Shift and Rotate logic • Because instruction set include 32-bit arithmetic and logical operators, the ALU must have two 32-bit inputs and one 32-bit output. • Execution of instruction such as AND, ADD will require that AC be connected to one ALU input and MD to the other. • If same adders is going to be used for INDEXING, IR register needs to be connected to one of ALU inputs and IX to the other. • Branch and Stack instructions require connection of PC and SP to ALU. Veton Këpuska

5. BUSSES • When a number of registers need to be connected to one or more targets, or • It is desired to use on Combinational Logic Unit with several sets of arguments, buses are appropriate solution. • ABUS & BBUS will be used to provide for interconnections between the two ALU inputs and the various registers. • OBUS is used to route output of ALU to any of registers. • “Three-bus” structure is almost standard in computers and is a derivative of a natural requirement to perform operations that combine two operands to produce a single result. • There is one more bus, carry input to the ALU, cin, which is effectively a 1-bit bus supplying a third argument to the adder within the ALU. Several possible sources may be connected to cin. • Interconnection structure RIC registers and ALU is depicted in the following slide. Veton Këpuska

6. CPU and MEMORY • CPU must be able to: • Send addresses and data to the memory, and • Receive data from memory • Addresses will normally pass through MA register. • An additional BUS is conveniently specified, ADBUS, to provide address path between the CPU module and the memory module. • Bi-directional data bus, DBUS, is provided as data bath between CPU and Memory. • During read cycle, the memory module will connect the desired data to the DBUS, which in turn can be clocked into the argument register, MD. • Note that SR (status register) is not shown in the following diagram of RIC. Veton Këpuska

7. 24 24 32 32 32 32 32 32 24 24 32 32 32 32 32 24 24 24 32 32 32 24 32 32 24 24 24 32 Basic Organization of RIC MEMORY ADBUS DBUS MA IR MD PC AC IX SP BBUS ABUS ALU cin OBUS Veton Këpuska

8. Register Transfers • The execution of an instruction by a computer consists of a series of • Transfers of data from register to register, • Data being processed by ALU as required. • Typically several such register transfers will be required to accomplish a single machine language insruction (e.g., MVT). • When registers are interconnected by BUSES, the execution of a single register transfer requires the generation of several control signals to connect the various buses and registers. • In RIC architecture signals must be generated to determine which: • Registers are placed on the buses, and • ALU output is gated into which register. • For example: a basic operation is the AND transfer, in which the contents of MD and AC are AND-ed and the result is placed in AC. The control signals and interconnections involved in this transfer are depicted in following figure of the next slide. Veton Këpuska

9. Example of Control Signals: AND transfer Veton Këpuska

10. AHPL Syntax of Bus Transfer • Actual Description of BUS transfer of the previous (AND Operation) example is: ABUS = MD; BBUS = AC; OBUS = ABUS∧BBUS; AC← OBUS; • Abbreviated AHPL syntax of Bus Transfer. It applies only in the case of single, unconditional transfers, where there generally is no ambiguity in determining the bus connections. AC← AC∧MD; • Care must be taken not to specify imposible connections like: AC← AC∧IX; Veton Këpuska

11. Memory Read and Write AHPL Statements • It will be assumed that memory: • Read operations are synchronous and that a memory word will be available at the same clock cycle in which the address is placed on ADBUS and the control line, read, is set to 1. ADBUS = MA; read = 1; MD←DBUS; • Write operations are likewise synchronous and that they will be carried out in same clock cycle, provided that write line is set to 1 at the same time as the address is placed on ADBUS and the word to be written is placed on DBUS. ADBUS = MA; write = 1; DBUS = MD; • Note that these statements do not describe the actual operations in the memory module. In the description (AHPL) of one module it can not be specified what happens in the other module. A complete system description will also include description of MEMORY module that is consistent with the assumptions made. Veton Këpuska

12. Fetch and Address Cycles • Ready for the first step in designing of a Control Unit for RIC, that is for writing of a control sequence. • Control Sequence is an AHPL program consiting of routines that execute RIC instructions. • The complete sequence of operations required to carry out a single instruction will be referred to as an instruction cycle. • Each instruction cycle will consist of at least two parts: • Fetch Cycle, and • Execute Cycle. • If the instruction includes an address, there will e one more part: • Address Cycle. Veton Këpuska

13. Fetch Cycle • During the fetch cycle, • The contents of the program counter, PC , are first shifted to memory address register, MA. • Program counter, PC, is incremented in preparation for the next instruction fetch. • Memory executes a read operation, placing the addressed word in MD register. • The instruction is then transferred from MD to IR (to be decoded). • Those steps are common to all instructions and are shown in following AHPL code: • MA← PC. • ADBUS = MA; read = 1; MD←DBUS; PC = INC(PC). • IR←MD. • Note that there are two separate operations in step 2. This is possible because the read from memory operation does not use the internal bus structure. Veton Këpuska

14. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OP 0 1 AD1 MODE AD2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OP 1 AM Address Decoding Fetched Instruction • Instruction after being fetched is now in IR register. However, first thing that is needed is to determine what kind of instruction it is: 32-bit or 2x 16-bin instructions. Recall that bit # 4 of the instruction specifies if it is 32-bit or 16-bit instruction. Veton Këpuska

15. 0111 1 CONDITIONS Displacement 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Decoding Fetched Instruction (2) • Following Branch instruction determines if instruction is a 32 or 16-bi instruction: • → (IR’[4])/(16-bit instruction sequence). • If control reaches step 5 the instruction is identified as 32-bit instruction. However, there are two basic types of instructions: • Branch Instructions: • 16-bit opcode and • 16-bit displacement. • All other instructions: • 8-bit opcode, and • 24-bit address. • Note that opcode IR[0:3]=0111 specifies the branch instructions. Thus testing for these bits we can branch to a sequence to implement branch instruction • NO DELAY → (IR’[0] ∧ IR[1] ∧ IR[2] ∧ IR[3])/(Branch sequence). Veton Këpuska

16. Address Cycle • If control reaches step 6, that specifies that the instruction is a 32-bit instruction with address. Therefore, address cycle can be started with this step with one exception. The exception is the case of immediate addressing whereby the address is really not an address rather it is an operand. • Recall the table specifying addressing modes in RIC: Veton Këpuska

17. Address Cycle (2) • Immediate Addressing: If bit 5, IR[5], is 1 that indicates that the instruction uses immediate addressing. Step 6 tests if this is not the case then the sequence skips step 7, otherwise immediate addressing is executed by sign extending the data. • NO DELAY;→ (IR’[5])/(8). • MD[0:7] ← (8 ⊤ 0)’ ∧MD[8];→ (22). Veton Këpuska

18. Address Cycle (3) • Address Mode Determination. • Step 8 tests for indirect addressing: • NO DELAY;(IR’[7])/(11). • If IR[7] = 1, then the indirect addressing cycle is entered at step 9, which moves the address portion of the instruction fro MD to MA. The address could just as well have been taken form IR, MD was used for consistency with later steps. Step 10 then reads the indirect address to MD. • MA← MD[8:3]; • ADBUS = MA; read = 1; MD← DBUS; Veton Këpuska

19. Address Cycle (4) • Step 11 in following AHPL code delivers the effective address, that is the actual address that will be used to access the operand, to MA. • This step could have been broken up into several steps, however, conditional transfer was used to shorten the sequence. • If IR[6] = 0, the address is moved directly from MD to MA. • If IR[6] = 1, the address is indexed before being moved to MA. • MA← (MD[8:31] ! ADD[1:24](MD[8:31]; IX)) * (IR’[6], IR[6]); • Start of execute cycle. Veton Këpuska

20. Example 6.1 • Rewrite step 11 making the bus connections explicit: • MA← (MD[8:31] ! ADD[1:24](MD[8:31]; IX)) * (IR’[6], IR[6]); • Solution: Using Figure in slide 7 as reference MD and IX registers are routed to the adder through the ABUS and BBUS respectively. Since there is no carry input cin must be connected to zero. • ABUS = MD; BBUS = (8 ⊤ 0),IX; cin ← 0;OBUS = (ABUS ! ADD[1:24](ABUS; BBUS; cin)) * (IR’[6], IR[6]);MA← OBUS[8:31]. Veton Këpuska

21. Execute Cycles for Addressed Instructions • In step 12 the instruction will be on of 15 addressed instructions to execute, with the effective address to be used in the instruction in MA. • One way to resolve those 15 cases is to have 15 way branch to separate sequences for each of the instructions. • More common approach is to divide the instructions into categories based on various common features. • To implement various branches, we first need to know the specific opcodes for the various instructions. The list of opcodes is given in the following table: Veton Këpuska

22. Opcodes for Addressed Instructions Veton Këpuska

23. Execute Cycles for Addressed Instructions • From other instructions we separate JMP and JSR, for which the address is not used to access memory but is transferred to PC as the address of the next instruction. • Recalling that step 5 separated opcode 0111 for the branch sequence, it suffices to check for IR[1:3] = 111 to identify JMP command. • NO DELAY;→(∧/IR[1:3])/(14). • PC← MA;→ (1). Veton Këpuska

24. Execute Cycles for Addressed Instructions • Step 13 executes JMP by transferring the effective address to PC and branching back to step 1 to fetch the new instruction. • If the instruction is not a JMP, control branches to step 14. At this step control separates for execution of the JSR instruction. The final subroutine address (after possible indexing or indirect addressing) was stored by step 9 in MA. • Before control is transferred to step 32 for execution of JSR, step 15 moves this address to IR[8:31] sot that MA is free for addressing the stack in the process of saving the current contents of PC. • NO DELAY;→(∧/IR’[0:2])/(16). • IR[8:31] ← MA; # to JSR→ (32). Veton Këpuska

25. Execute Cycles for Addressed Instructions • The logic implementing this last branch decision takes advantage of the fact that the values of IR[0:3] specifying JMP are now don’t cares (they have been covered previously) as those for BRA. Since JSR instruction involves the stack, we shall defer further discussion of this instruction until later, when stack operations are covered. • Once control reaches step 16, it is known that the address formed in MA will be used to access memory. All instructions, except MVF, start by reading memory, so a branch is specified at this step to separate MVF. • NO DELAY→(IR[0]∧IR[2])’/(19). • MD← AC; • write = 1; ADBUS = MA; DBUS = MD;→ (1). • Step 16 branches to step 19 if the command is not MVF, • Steps 17 and 18 execute MVF by moving the contents of AC to MD and then writing them to memory. Veton Këpuska

26. Execute Cycles for Addressed Instructions • Step 19 brings the operand to MD. • ABUS = MA; MD ← DBUS; read = 1; →(IR[0]∧IR[1])’/(22). • At step 19, the hardware control process is ready to execute any of the 13 instructions involving an operand from memory, of which 11 involve the accumulator. • Separated for execution by step 20 are the two instruction that do not use the accumulator, INC and DEC. The implementation of step 19 takes advantage of the fact that the value of IR[0:3] specifying JMP and JSR are covered previously (e.g., are “don’t care”). • MD← (INC(MD) ! DEC(MD)) *(IR’[3], IR[3]);zff←∨/OBUS; nff←OBUS[0]. • write = 1; ADBUS = MA; DBUS = MD;→ (1). Veton Këpuska

27. Execution of an Instruction • Operands are in AC & MD Register • Operation is performed by ALU as determined by opcode. • Result is placed on OBUS, and • Data is routed back to AC with exception of CMP and BIT operations. • Important Note: • Operand in MD is obtained in an unique way depending on addressing mode applied (immediate, direct, indirect, indexed, indirect indexed). Veton Këpuska

28. Execution of an Instruction • ALU consists of: • A set of logic units that perform operations: • ADD • AND • OR • XOR • ABUS and BBUS are permanently connected to the inputs of those units. • Connections to those buses, and • Connections to the appropriate ALU output to the OBUS is determined by the operation to be executed. Veton Këpuska

29. ALU Operations defined by 32-Bit Instruction set ADD = ADD(ABUS, BBUS, cin) Veton Këpuska

30. Karnough Map of Instructions Opcode • From Table in slide 22, (Table 6.3 in the book) Veton Këpuska

31. Connection Control to ALU • ABUS: MD vs. MD’ ABUS = (MD, MD’)*((IR’[0]∧ IR’[1])∧ (IR’[2]∨IR[3])’, (IR’[0]∧ IR’[1])∧ (IR’[2]∨IR[3])); Veton Këpuska

32. Connection Control to ALU • BBUS: • BBUS = AC; • cin = (cff∧IR’[3])∨(IR’[1]∧IR[3]); Veton Këpuska

33. Connection Control to OBUS • ADD - Operation • OBUS = ADD(ABUS;BBUS;cin)* (IR’[0]∧IR’[2])∨(IR’[0]∧IR[3]); Veton Këpuska

34. Connection Control to OBUS • AND - Operation • OBUS = (ABUS∧BBUS)*(IR[0]∧IR[3]); Veton Këpuska

35. Connection Control to OBUS • OR - Operation • OBUS = (ABUS∨BBUS)*(IR[0]∧IR’[2]∧IR’[3]); Veton Këpuska

36. Connection Control to OBUS • XOR - Operation • OBUS = (ABUS⊕BBUS)*(IR[0]∧IR[2]∧IR’[3]); Veton Këpuska

37. Connection Control to OBUS • ABUS - Connection • OBUS = (ABUS)*(IR’[0]∧IR[2]∧IR’[3]); Veton Këpuska

38. OBUS Clocking • Content of OBUS gets transferred to AC with exception of CMP and BIT operations. • AC*(IR[2]∧IR[3]) ← OBUS; Veton Këpuska

39. Carry Flag • Carry flag, cff, is affected only by four add and subtract operations as well as INC and DEC. • cff*(IR’[3]∧(IR’[1]∧IR[0])) ← ADD[0](ABUS;BBUS;cin); Veton Këpuska

40. Zero and Negative Flag • Zero flag is set when all bits in the bus are zero. • zff← (∨/OBUS)’; • Negative flag, nff, is set when sign bit (OBUS[0]) is 1. • nff← (OBUS[0]); • Overflow flag, vff, is set when the sign of two operands is are the same but the sing of the result is different. This flag is affected with the same operations as cff. Note that buses are 32 bit while output of ALU is 33 bit. • vff*(IR’[3]∧(IR’[1]∧IR[0])) ← (ABUS[0]∧BBUS[0]∧(ADD[1](ABUS;BBUS;cin))’);(ABUS’[0]∧BBUS’[0]∧(ADD[1](ABUS;BBUS;cin))); Veton Këpuska

41. Putting it all Together: • ABUS = (MD, MD’)* ((IR’[0]∧ IR’[1])∧ (IR’[2]∨IR[3])’, (IR’[0]∧ IR’[1])∧ (IR’[2]∨IR[3])); BBUS = AC; cin = (cff∧IR’[3])∨(IR’[1]∧IR[3]); OBUS = ADD(ABUS;BBUS;cin)* (IR’[0]∧IR’[2])∨(IR’[0]∧IR[3]); OBUS = (ABUS∧BBUS)*(IR[0]∧IR[3]); OBUS = (ABUS∨BBUS)*(IR[0]∧IR’[2]∧IR’[3]); OBUS = (ABUS⊕BBUS)*(IR[0]∧IR[2]∧IR’[3]); OBUS = (ABUS)*(IR’[0]∧IR[2]∧IR’[3]); AC*(IR[2]∧IR[3]) ← OBUS; cff*(IR’[3]∧(IR’[1]∧IR[0])) ← ADD[0](ABUS;BBUS;cin); zff← (∨/OBUS)’; nff← (OBUS[0]); vff*(IR’[3]∧(IR’[1]∧IR[0])) ← (ABUS[0]∧BBUS[0]∧(ADD[1](ABUS;BBUS;cin))’) ∨(ABUS’[0]∧BBUS’[0]∧(ADD[1](ABUS;BBUS;cin))); → (1). Veton Këpuska

42. Register Only (16-bit) Instructions • 16-bit instructions have IR[4] = 0; • Step 4 in control sequence branches to handle those instructions. • Packing two 16-bit instructions in one fetch cycle is necessary otherwise there is no advantage of using this feature. • When 2 16-bit instructions are fetched: • Upper 16-bits will be processed first in the same manner as the 32-bit instruction. • Instead of going back to fetch another instruction the next instruction is processed. • There are two ways that this can be accomplished (e.g. processing second 16 –bit instruction): • Performing decoding in place – this solution implies extra hardware to accomplish it. • Shifting upper 16-bits to lower half of 32-bit Word – this solution uses the same hardware to decode the instruction with added expense of shifting. • RIC uses 2’nd solution. • To keep track of upper/lower half of each 16-bit instruction a second half flag, shf, is used. Se the flow chart bellow: Veton Këpuska

43. Register Only (16-bit) Instructions • Fetch Sequence for 16-bit Instructions: 1-3 FETCH INST. shf ← 0; 4 Yes 16-BIT 5-49 No Execute 32-BIT 50-99 Execute 32-BIT 100 1 shf 0 101 IR[0:15] ← IR[16:31] shf ← 1 Veton Këpuska

44. Interpretation of 16-bit Instructions • Separate Register-Only instructions from the rest. • Register only instructions all operations listed in Table presented in the next slide (Fig 6.8. in the book). • Note that opcode is identical to 32-bit instructions (no additional decoding hardware required) with exception of MVF that was replaced by shift/rotate instruction. • In addition format of 16-bit instruction is repeated for convenience. • Let RFN(AD1) and RFN(AD2) represent the registers specified by AD1 and AD2 respectively. • Two operand instructions (ADD, AND) can be generalized as: • RFN(AD1) ← RFN(AD1) ⊙ RFN(AD2); • ⊙ stands for logical or arithmetic operation as specified by opcode. • Example MVT will be: • RFN(AD1) ← RFN(AD2) • Since AD1 and AD2 can both specify any register, there is no need for the MVF. Its opcode is used for shift/rotate instruction. Veton Këpuska

45. Register Only 16-bit Instructions • 16-bit Register Only Instructions Veton Këpuska

46. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OP 0 1 AD1 MODE AD2 { } 0000 = AC 1000 = IX 1111 = SP 0000 = AC 1000 = IX 1111 = SP Two-Address Instruction Format { 00 = Register Mode 10 = Immediate Quick (IMQ) => AD2 = 4-bit Immediate Operand Veton Këpuska

47. Register Only 16-Bit Instructions • It was noted earlier that RIC architecture will not permit direct execution of an operation such as: • AC ← AC ∨IX; AC and IX registers are both on the BBUS. • Desired result can be achieved by first routing the contents of the register specified by RFN(AD2) to MD (which is connected to ABUS). • Also, immediate quick (IMQ) operand is in register specified by AD2. This instruction is in IR register. IR register is also connected to ABUS. • Thus, for two-operand instructions, AD1 will specify the operand that is on BBUS while AD2 will specify the operand on ABUS. • To understand branches of AHPL code, map of opcodes for register-only instructions is depicted. Veton Këpuska

48. Register Only 16-Bit Instructions • Opcodes for Register-Only Instructions • Note opcodes with IR[0:1] = 11 are not used, thus can be treated as don’t cares. Also it will be assumed that Opcode 0111 will not be used thus it can be treated as don’t care. Veton Këpuska

49. Register Only 16-Bit Instructions • The first branch of the 16-bit sequence will be: • → (IR[0] ∧IR[1])/(other 16 bit instruction) • Shift/Rotate Sequence may be written as follows: • NO DELAY→ (IR[1] ∧IR[2])/(Shift/Rotate) Veton Këpuska

50. Shift/Rotate • (IR[1] ∧IR[2]) Veton Këpuska