Turbo decoder Core For ASIC&System Development

1. Turbo decoder CoreFor ASIC&System Development softDSP Corporation 1999-2000

2. Turbo code • Offers near idealistic, Shannon-limit Error correction performance • This great coding capability has lead turbo codes to the standard of 3rd generation wireless mobile communications (3GPP)

3. softDSP Turbo decoder • Fully Implemented with VHDL and offer flexible interface for use in various applications such as.. • 3GPP, Power-line modem, Military comm. Magnetic-storage channel, Satellite comm. High-speed wireless comm. Etc.

4. Features • Use max-log-MAP decoding method as an internal component decoder • Use sliding-window technology to reduce memory size • 3GPP compliant (block size 40-5114) • Constraint length K=4, Rate ½, 1/3 • 5bit input (4-8bit) and internal 8bit processing • Easy external I/O interface • Easy to modify code to your system

5. What we offer?(Offering Materials) • VHDL Source code • Turbo code simulation C-source (floating/fixed point) • 3GPP standard interleaver generation C-source (3G TS 25.212 V.3.2.0) • Turbo decoder test vector • Designer’s guide file

6. Entire Turbo decoder Core Structure • MAP decoder • FIFO memory • LLR memory • Turbo controller • SNR scaler • Additional circuitry

7. system FIFO logic SNR scaler + parity MAP decoder llr_out - out_clk LLR memory 1 Num_iter MUX MUX LLR memory 2 SNR DFF Swap Parity alternate First Iter Rd_address Intaddr_require Int_deint Blocksize_2 MUX Turbo_ctrl output_clock rd_clk DFF data_enable Interleaver address Int/deint SNR reset start Interleaver/Deinterleaver blocksize iteration

8. Swap 13 System Address I/O Interface of Turbo decoder core 8 System Data 4 Number of MAP Iteration 13 Parity Address Parity Alternate flag 8 Parity Data 8 Decoded LLR Output 3 SNR 13 Output Enable Block Size Output Data Clock 13 Block Size2 4 Iteration Reset Data Enable Start CLK Rd_clk Notwr_clk 13 Intaddr_require Interleaver_address 13 Int_deint

9. Decoding Operation Normal vs. Sliding-window READ READ READ WRITE WRITE WRITE (a) Normal Turbo(MAP) decoding operation READ READ READ READ READ WRITE WRITE WRITE WRITE WRITE (b) Sliding-window decoding operation

10. Procedure of system operation • Easy to control : Just by reset and start signal • Turbo decoder operates as a slave device of the master processor • Turbo decoder generate address signal and get the data and decode it • You can extract decoded output just when output clock is validated

11. Disable Reset signal By asserting start signal, Let the Turbo decoder start decoding Supply System/Parity data and Interleaver address Get the decoded output If decoding of current block ended? The re-assert start signal Initialize Blocksize / Iteration / SNR information Register Memory read address / Interleaver address require signal Get the data & decode it Blocksize, Iteration, SNR Operation of Turbo decoder Operation of external processor

12. SoftDSP Turbo decoder core Reset Application system design Start Blocksize/Iteration/SNR Host processor Output data clock Interleaver_address Output data Intaddr_require Iteration Number Int/deint System_data System_address Parity_data Interleaver memory Parity_address Parity_alternate System data memory Parity data memory From equalizer/ RAKE receiver/ AGC etc

13. 1-iteration 2-iteration 3-iteration

14. Overall System specification • Critical path: reduce to two 8bit adder (CLA) and two 8bit comparator (Wallace type) including slight counter overhead • Gate count: About 24K except memory • Performance: shows nice performance over 3dB (Eb/N0)