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Lecture #3 VLSI Design

Lecture #3 VLSI Design. MOSFET Fundamentals. N -channel M etal O xide S emiconductor F ield- E ffect T ransistor. NMOS Transistor. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +. +.

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Lecture #3 VLSI Design

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  1. Lecture #3 VLSI Design Lecture #3

  2. MOSFET Fundamentals N-channel Metal Oxide Semiconductor Field-Effect Transistor NMOS Transistor Lecture #3

  3. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + The MOS Capacitor Less Positive More Positive Much More Positive n n << Ions V < VT n >> Ions V > VT n Ions V  VT VT Minimum Voltage for Inversion Lecture #3

  4. NMOS Transistor Lecture #3

  5. PMOS Transistor Lecture #3

  6. nMOS with VG < VT0 VD = 0 Lecture #3

  7. nMOS with VG > VT0 VD = 0 Lecture #3

  8. Regions of Transistor Operation 1. Linear region:VDS < VGS – VT VT - threshold voltage (Min voltage to form inversion layer) 2. Saturation region: VDS  VGS - VT Read Text (Sections 3.2.2, 3.2.3, 6.2) Lecture #3

  9. nMOS - Linear Region with VG > VT0 VD < VG –VT0 Lecture #3

  10. Current Equation - Aspect Ratio - Device Transconductance - Process Transconductance - Gate Cap / Unit area - Mobility of carriers Permitivity of SiO2 • Rel. Permitivity = 3.9 • Permitivity of free space =8.85410-14 F/cm tOX-Gate Oxide Thickness = 2000A=20nm COX = 1.725fF/m2 Lecture #3

  11. Lecture #3

  12. 1.5V Lecture #3

  13. nMOS in Saturation VG > VT0 VDS >VG –VT0 1.5V Lecture #3

  14. b • • 1.5V c • a At ‘a’ At ‘b’ At ‘c’ Lecture #3

  15. For NMOS For PMOS Lecture #3

  16. Channel Length Modulation Lecture #3

  17. Channel Length Modulation 0.005 0.02V-1 Lecture #3

  18. MOSFET Symbols Lecture #3

  19. |V | GS R on |V | > |V | GS T |V | < |V | GS T Switch Model of CMOS Transistor Lecture #3

  20. Vout Vin Vout VDD V f OH V(y)=V(x) Switching Threshold Vth VIN VOUT V OL Vin V V OL OH Nominal Voltage Levels Inverter DC Operation Voltage Transfer Characteristic Vth =? Lecture #3

  21. V in 50% t t t pHL pLH V out 90% 50% 10% t t t f r Delay Definitions Lecture #3

  22. CMOS Inverter: Steady State Response VDD VDD RON V = V OH DD VOUT VOUT V = 0 OL Threshold Voltage V = f(R , R ) RON th onn onp VIN = VDD VIN = 0 Lecture #3

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