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Power supply per Fisica delle Alte Energie: problematiche e soluzioni innovative

Explore innovative power distribution architectures and supply requirements at LHC experiments, including serial and parallel powering solutions, and DC-DC converter topologies for Point of Load converters.

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Power supply per Fisica delle Alte Energie: problematiche e soluzioni innovative

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  1. Power supply per Fisica delle Alte Energie: problematiche e soluzioni innovative B.Allongue1, G.Blanchot1, S.Buso2, F.Faccio1, C.Fuentes1,3, P.Mattavelli2, S.Michelis1,4, S.Orlandi1, G.Spiazzi2 1CERN – PH-ESE 2Dept. Information Engineering, Padova University, Italy 3UTFSM, Valparaiso, Chile 4EPFL, Lausanne

  2. Outline Present power distribution architectures at LHC experiments Expected power supply requirements for the future LHC upgrade Serial powering Parallel powering: DC-DC converters based solution DC-DC converter topologies for Point of Load (POL) converters Conclusions

  3. Present Power Distribution Schemes in Trackers (ATLAS) PS Patch Panels (passive connectors) Typical low-voltage power distribution in LHC trackers: No on-detector conversion. Low-voltage (2.5-5V) required by electronics provided directly from off-detector. Sense wire necessary for PS to provide correct voltage to electronics. Cables get thinner when approaching the collision point (strict material budget). • In view of SLHC: • Scheme not easily scalable to the larger currents expected (see next slides)

  4. Present Power Distribution Schemes in Trackers (ATLAS) 1A/channel (analog or digital), round-trip cables, and sense to nearest regulation 100m 13-15m 0.5-2m AC/DC DC/DC PP (with “LDO” in some cases) PP PP Module AC/DC DC/DC 100m 0.5-2m PP PP PP Module 0.5-2m PP PP Module 0.5-2m PP PP Module

  5. Example: LAr Calorimeter Power Supply

  6. Example: LAr Calorimeter Power Supply Total power: 3 kW Output voltages: Vout1 = +6V – 100A Vout2 = +11V – 20A Vout3 = +7V – 160A Vout4 = +6V – 150A Vout5 = +4V – 130A Vout6 = -4V – 180A Vout7 = +7V – 15A Low Drop-Out (LDO) regulators on board

  7. Example: CMS Power Supply Architectures Source: S. Lusin, TWEPP ‘07

  8. Don’t get 5 or 10 times more cables in Power efficiency is too low (50% ATLAS SCT  ~15% SLHC) Cable material budget Packaging constraints Why independent powering fails at SLHC ? Source: M. Weber, TWEPP ‘07

  9. Example: ATLAS Tracker All ASICs will be manufactured in an advanced CMOS (or BiCMOS) process, 130nm generation or below. Here we consider only CMOS ASICs. Detector module • Front-End readout ASIC • Idigital≥ Ianalog (for instance, current projection for ATLAS Short Strip readout is Ianalog~ 20mA, Idigital ~ 60-100mA) • 2 power domains: Van=1.2V, Vdig=0.9-0.8V (as low as possible) • Clock gating might be used => switching load Detector • Hybrid/Module controller • Ensures communication (data, timing, trigger, etc.) • Digital functions only • It might require I/Os at 2.5V Read-out hybrid Rod/stave Other than the rod/stave controller, optoelectronics components will also have to be used, requiring an additional power domain (2.5-3V) Source: S. Michelis, TWEPP ‘07

  10. Example: ATLAS Tracker Large waste of power if Van=Vdig=1.2V Large current increase (Power on cables = RI2) • Summary • 3 Voltages to be provided to minimize power consumption: • 2.5V for optoelectronics and (maybe) control/communication ASICs • 1.2V for analog circuitry in FE ASICs • 0.8-0.9V for digital circuitry in FE ASICs. This domain uses most of the current! • Digital current might be switching in time (to really minimize the power) • Power and Current in LHC/SLHC • Projection based on current estimate for ATLAS upgrade • Only accounting barrel detector, power from Readout ASICs only • SCT is LHC ATLAS Silicon Tracker detector, to be replaced (grossly) by Short Strip layers in present upgrade layout Source: S. Michelis, TWEPP ‘07

  11. Working Environment • High magnetic field (up to 4T in CMS, 2T in ATLAS) • High level of radiation inside the detectors: • LHC doses probably increased x 5 – 10 so we can extrapolate to hundreds of Mrad in several Tracker location, decreasing to ten(s) in the outer Trackers

  12. Power Distribution Schemes • Serial Powering (SP) • Shunt regulators • Parallel Powering (PP) • Inductor-based switching converters • Switched capacitor converters

  13. Serial Powering Powering schemes comparison Efficiency:= Example of efficiency plot vs. number of modules (n) and supply voltage (V) for Im = 2 A Rc = 3 Ω for Serial Powering scheme Pc = Im2Rc PM = nImVm Source: G. Villani, TWEPP ‘07

  14. Shunt Regulation in SP External shunt regulator + external power transistor Load Constant current source Load Source: G. Villani, TWEPP ‘07

  15. Parallel Powering Example of LAr calorimeter power supply niPOL = Non-Isolated Point of Load Converters

  16. Reduction of Cable Power Losses Converter Ratio N V I N V I/N V2 I2 Converter 2 R Solution without converter: • Power losses on cable = Solution with converter: • Power losses on cable =

  17. Power supply for ATLAS Trackers • The high magnetic field calls for coreless conversion stages • Low-value air core inductors can be used with switching frequencies in the megahertz region • Inductor-less conversion stages can also be used (switched capacitor converters) • Switching noise is a big concern Soft-switching is a must!

  18. Different Converter Topologies (1/3) Rload Co Co Rload • Single phase synchronous buck converter • Simple, small number of passive components • Larger output ripple for same Co • RMS current limitation for inductor and output capacitance • 4 phase interleaved synchronous buck converter • Complete cancellation of output ripple for a conversion ratio of 4 (with small Co) • Smaller current in each inductor (compatible with available commercial inductors) • Large number of passive components • More complex control circuitry L1 Ug uo Q1 Q2 L1 Ug uo Q1 Q2 L2 Q3 Q4 L3 Q5 Q6 L4 Q7 Q8

  19. Different Converter Topologies (2/3) u S + i i r C F L1 S S2 S1 L L Q r F + + iL1 + U D Ug + C u u R g uo F D o uC1 o S4 C C1 Co Ro D iC1 L2 iL2 S3 • Two phase interleaved synchronous buck converter with integral voltage divider • Complete cancellation of output ripple for a conversion ration of 4 (with small Co) • Simpler control and smaller number of passive components than 4 phase interleaved • More components than the single-phase synchronous buck • Multi-resonant buck converter • Very small switching losses (zero voltage and zero current switching) • To achieve resonance: • Current waveforms have high RMS value => large conduction losses => lower efficiency • Voltage waveforms have high peaks, possibly stressing the technology beyond max Vdd • Different loads require complete re-tuning of converter parameters

  20. Different Converter Topologies (3/3) i g Q + 1 i C x 1 Q I 2 o + U v g x C Q x 3 + u Load C o 2 Q 4 • switched capacitor voltage divider • rather simple, limited number of passive components • lack of inductor => good for radiated noise and for compact design • No regulation of the output voltage, only integer division of the input voltage • Efficiency decreases with conversion ratio (larger number of switches) • Good solution for ratio = 2, for which high efficiency can be achieved

  21. Single-phase Synchronous Buck Converter t iS1 L S1 Ug uDS2 uo iL iS2 + Ug Co S2 Ro t 0 Principle of operation The 2°order L-Co filter removes the switching frequency harmonics, making the output voltage DC component dominant

  22. Single-phase Synchronous Buck Converter t iS1 iL uL S1 iL L uo iS2 + Ug Co S2 Ro t iS1 t iS2 t 0 • Hp: constant voltages Inductor flux balance:

  23. Single-phase Synchronous Buck Converter Co1 L ux t iL uo S1 + Ug Co S2 iL Ro Co2 t iS1 S1 = S2 = off D1 = on t iS2 uDS2 Ug t 0 Ug uDS1 Tdead • Quasi-square wave operation Zero Voltage Switching turn on High current ripple

  24. Multiphase Interleaved Buck Converters L SH1 + ug uo C SL1 L SH2 - SL2 SH3 L SL3 N = phase number Same drive signal but phase shifted by Tsw/N • Reduced current level per phase • Reduced output current ripple • Reduced input current ripple • Increased bandwidth (Feq=N Fsw)

  25. Multi-Phase Interleaved Converters Ripple reduction on output filter iLtot L SH1 Example: 2 phases + iL1 ug uo C SL1 L SH2 - iL2 SL2 iL1 Io/2 Fsw iL2 Io/2 Fsw iLtot Io 2·Fsw

  26. Output Current Ripple Cancellation 12 V 5 V Vo=1.3 V Input voltage 12 V 5 V Vo=1.3 V 1 0.9 0.8 0.7 Two phases 0.6 Ripple Ratio 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Duty cycle D=0.5 for the best cancellation effect 1 0.9 0.8 0.7 Four phases 0.6 Ripple Ratio 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Duty cycle D=0.25, 0.5, 0.75 for the best cancellation effect

  27. Multi-Phase Interleaved Converters Ripple reduction on input current 2·Fsw Io/2 ig iLtot L SH1 + is1 iL1 ug uo C SL1 L SH2 - is2 iL2 SL2 iL1 is1 Io/2 Fsw is2 iL2 Io/2 Fsw ig

  28. Multi-resonant buck converter u S + i i r C F S L L Q r F + + U D C u u R g F D o o C D Example: Input voltage: Ug = 12V Output voltage: Uo = 3V Output current: Io = 3A Switching frequency: fS = 6.4MHz Resonant inductance: Lr = 100nH Switch capacitance: CS = 3nF Diode capacitance: CD = 9nF uS uD iF ir

  29. Two-Phase Interleaved Buck with Voltage Divider S1 S2 L1 + i1 + Uin S4 Uo R Co UC1 C1 - - L2 i2 S3

  30. Two-Phase Interleaved Buck with Voltage Divider t t iL2 t iL1 t iC1 iL2 t -iL1 iL1+iL2 t 0 D<0.5 D>0.5 t t iL2 t iL1 t iC1 iL2 t -iL1 iL1+iL2 t 0

  31. Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 L1 S2 S1 iL1 + Uin + uo uC1 S4 C1 Co Ro iC1 L2 iL2 S3 t t iL2 t iL1 t iC1 iL2 t -iL1 iL1+iL2 t 0

  32. Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 L1 S2 S1 iL1 + Uin + uo uC1 S4 C1 Co Ro iC1 L2 iL2 S3 t t iL2 t iL1 t iC1 iL2 t -iL1 iL1+iL2 t 0

  33. Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 L1 S2 S1 iL1 + Uin + uo uC1 S4 C1 Co Ro iC1 L2 iL2 S3 t t iL2 t iL1 t iC1 iL2 t -iL1 iL1+iL2 t 0

  34. Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 L1 S2 S1 iL1 + Uin + uo uC1 S4 C1 Co Ro iC1 L2 iL2 S3 t t iL2 t iL1 t iC1 iL2 t -iL1 iL1+iL2 t 0

  35. Steady-state analysis (D < 0.5) • Inductor flux balance: • Capacitor charge balance:

  36. Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 • “Natural” current sharing • Optimal ripple cancellation for overall voltage conversion ratio equal to ¼ • Reduced switch voltage stress (one half of input voltage)

  37. Two-Phase Interleaved Buck with Voltage Divider: D > 0.5 • Unequal average currents in the two phases • Increased switch voltage stress (equal to the input voltage)

  38. Two-Phase Interleaved Buck with Voltage Divider: D < 0.5 iC1 0 D=0.37 iL1+iL2 iL1 iL2 0

  39. Two-Phase Interleaved Buck with Voltage Divider: D > 0.5 D=0.63 iL1+iL2 iC1 iL1 iL2 0 0

  40. Switched-Capacitor Voltage Divider ig Q1 + ix C1 Q2 Io + Vg vx Cx Q3 + vo Load C2 Q4 ig ig i1 i1 ix R + + C1 + C1 vx Cx Vg Vg i2 Io ix i2 Io R + + vo C2 + vo C2 vx Cx Topology corresponding to Q1, Q3 = “on”; Q2, Q4 = “off” Topology corresponding to Q2, Q4 = “on”; Q1, Q3 = “off” R = 2RDSon+RESRx C1 = C2 = C

  41. SCVD: Steady-State Analysis • Input voltage: Vg = 3V • Output current: Io = 0.1A • Switching frequency: fS = 200kHz • MOSFET on resistance: RDSon = 100mW • Filter capacitors: C = 200nF • Charge transfer capacitor: Cx = 10mF vx Vg/2 ig vo ix

  42. SCVD: Steady-State Analysis Converter efficiency as a function of output current total parasitic resistance R = 2xRDSon for four different output current values: Io = 0.1 A (red curve); Io = 0.2 A (blue curve); Io = 0.3 A (green curve); Io = 0.4 A (magenta curve) (C = 200nF, Cx = 10mF)

  43. 2PIB-VD: Experimental Results atfs = 1MHz Input voltage: Ug = 12 V Output voltage: Uo = 2.5 V Nominal output power: Po = 7.5W Nominal output current: Io = 3A

  44. 2PIB-VD: Experimental Results atfs = 1MHz L1 S2 S1 iL1 + Ug + uo uC1 S4 C1 Co Ro iC1 L2 iL2 S3 Converter’s main waveforms at nominal power: S3 logical driving signal (Blue); output voltage ripple (yellow); S3 Drain-to-Source voltage (red)

  45. Single Buck Converter: Experimental Results at fs = 1MHz Input voltage: Ug = 12 V Output voltage: Uo = 2.5 V Nominal output power: Po = 7.5W Nominal output current: Io = 3A Lower Inductance value Parallel-connected switches

  46. Single Buck Converter: Experimental Results at fs = 1MHz Quasi-square wave operation Converter’s main waveforms at nominal power: S1 logical driving signal (Blue); output voltage ripple (yellow); S3 Drain-to-Source voltage (red) Effect of output cap ESR

  47. Efficiency Comparison at fs = 1MHz C1 = 2x470nF C1 = 2x220nF Coilcraft L Home-made L Home-made L: 0.84mm wire diameter (L = 220nH, 50mW) wound on a plastic support (f = 4.38mm)

  48. Experimental Results at fs = 2MHz 2PIB-VD Single buck

  49. Efficiency Comparison @ fs = 2MHz

  50. Conclusions Summary The present power supply architecture at LHC will no longer be sustainable in the future upgrades Distributed power supply architectures based on DC-DC converters are proposed High step-down ratio topologies are the key for increasing power distribution with the same cabling High conversion efficiency as well as low switching noise are mandatory Future investigations Radiation tolerance components and technologies must be selected More intensive investigations on switching noise effects must be carried out

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