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Unit-I

Unit-I. Advanced Processors ARM7,ARM9 & ARM11 Processors. Contents. Introduction to ARM processors and it’s versions ARM7,ARM9 &ARM11 features Advantages and suitability in embedded application Registers, CPSR,SPSR ARM and RISC design philosophy ARM7 data flow model Programmers model

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Unit-I

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  1. Unit-I Advanced Processors ARM7,ARM9 & ARM11 Processors

  2. Contents • Introduction to ARM processors and it’s versions • ARM7,ARM9 &ARM11 features • Advantages and suitability in embedded application • Registers, CPSR,SPSR • ARM and RISC design philosophy • ARM7 data flow model • Programmers model • Modes of operations • Introduction to Tiva TM4C123G series overview • Programming model • Tivaware Library

  3. Contents • Introduction to ARM processors and it’s versions • ARM7,ARM9 &ARM11 features • Advantages and suitability in embedded application • Registers, CPSR,SPSR • ARM and RISC design philosophy • ARM7 data flow model • Programmers model • Modes of operations • Introduction to Tiva TM4C123G series overview • Programming model • Tivaware Library

  4. ARM and RISC design philosophy Key Points to discuss…. 1. Processor performance measures (Speed, throughput and Peripheral Interaction) • Pipeline advancements • Core Vs. Controller /Processor • Why RISC architecture ? • Architecture Evolution is towards applications

  5. Quick Review of CISC • Fast context switching (smaller process environment to handle) • Powerful assembly language programming facility • Reduced requirements on compiler design (machine language forms a layer of abstraction) • Flexibility of processor operation via microcode modifications (writable control store or ROM change) • Powerful and fast floating-point operations (highly sophisticated instructions) • Reduced memory requirements (programs require less memory) • Improved cache performance (due to smaller program size) • Reduced bus traffic (highly sophisticated instructions require less memory access to do the same job)

  6. RISC Features • Large register files • Emphasis on register-oriented operations • Instructions that primarily execute in a single cycle • Simple LOAD/STORE instructions for memory access • Limited addressing modes • Fixed-length instructions that do not span word boundaries • Hard-coded logic (as opposed to microcode driven) • Pipelined instruction cycle (typically uniform delay pipelines)

  7. RISC Advantages….. • Fast instruction execution (simple compact instructions; surveys show most often used) • Simple control unit (less instructions and addressing modes to be handled) • Fast decode (limited instructions and addressing modes; fixed size instructions) • Highly efficient pipelined parallel execution (fixed-length and simple instructions) • Faster processor design, development, and test (simpler design) • Fast instruction execution (simple compact instructions; surveys show most often used)

  8. RISC Advantages….. • Improved optimizing compiler support (simple machine language generally preferred) • Reduced pipeline branching penalties (due to delayed branch technique used in many RISCs) • Improved subroutine parameter passing speed (register windows) • …………………………………………………………..

  9. Comparison at a glance

  10. RISC Design Philosophy • Instruction • Pipeline • Registers • Load and store

  11. Early days Today's trend

  12. ARM Design Philosophy advantages /Suitability towards Embedded System Hardware Aspect (Technology Perspective) • Low Power • High code density • Reduced die area • Adoption of standard bus architecture • Hardware debug technology

  13. ARM Design Philosophy advantages /Suitability towards Embedded System Software Aspect (Developers’ Perspective) • Variable cycle executions for certain Instructions • Inline barrel shifter • Thumb Instruction • Conditional Execution • Enhanced Instructions

  14. Typical Embedded Hardware

  15. Typical ARM Feature.. • Large Uniform Register file • Load /store architecture • Simple addressing modes • Uniform and simple Instruction fields

  16. NonRISC ARM features • Control over both the Arithmetic Logic Unit(ALU) and shifter in every data-processing instruction to maximize the use of an ALU and a shifter. • auto-increment and auto-decrement addressing modes to optimize program loops • Load and Store Multiple instructions to maximize data throughput • conditional execution of all instructions to maximize execution throughput. • Orthogonal instruction Set

  17. ARM Versions

  18. Development of the ARM Architecture 5TE Improved ARM/Thumb Interworking CLZ 4 Jazelle Java bytecodeexecution 5TEJ Halfword and signed halfword / byte support System mode 1 ARM9EJ-S ARM926EJ-S SA-110 Saturated maths DSP multiply-accumulate instructions 2 SA-1110 ARM7EJ-S ARM1026EJ-S 3 6 SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support ARM1020E Thumb instruction set 4T XScale Early ARM architectures ARM7TDMI ARM9TDMI ARM9E-S ARM720T ARM940T (MPU) ARM966E-S ARM1136EJ-S

  19. ARM Processor Nomenclature • ARM {x}{y}{z}-{T}{D}{M}{I}{E}{J}{F}{S} • X: family, • y: Memory Mangmt/Protection, • Z : Cache • I : Embedded ICE macrocell • F: Vector floating point unit • S: Synthesizable version ( Core is provided as source code and used by EDA tools)

  20. ARM9 Features • Von Neuman Harvard Architecture (modified Harvard) • 3 stage pipeline 5 stage pipeline • Enhanced clock speed (x2) • Faster load and store • Exposing pipeline interlock (support of compiler optimization) • Memory management and protection • ARM Jazelle technology which enables the direct execution of 8-bit Java byte code in hardware

  21. ARM11 Features • SIMD instructions (which can double MPEG-4 and audio digital signal processing algorithm speed) • Cache is physically addressed (solving many cache aliasing problems and reducing context switch overhead) • Unaligned and mixed-endian data access is supported • Reduced heat production and lower overheating risk • Redesigned pipeline, supporting faster clock speeds (target up to 1 GHz) • Longer: 8 (vs 5) stages • Out-of-order completion for some operations (e.g. stores) • Dynamic branch prediction/folding (like XScale) • Cache misses don't block execution of non-dependent instructions • Load/store parallelism • ALU parallelism • 64-bit data paths • Accelerated IRQ response • Vector floating point unit

  22. ARM Core (Data flow model)

  23. ARM Operating modes --- User : unprivileged mode under which most tasks run • FIQ : entered when a high priority (fast) interrupt is raised • IRQ : entered when a low priority (normal) interrupt is raised • Supervisor : entered on reset and when a Software Interrupt instruction is executed • Abort : used to handle memory access violations • Undef : used to handle undefined instructions • System : privileged mode using the same registers as user mode

  24. ARM Processor Modes

  25. Programmers Model Spsr is Available in All modes Except user.

  26. Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers r0 r0 r0 r0 r0 r0 r0 Abort Mode SVC Mode Undef Mode FIQ Mode User Mode IRQ Mode r1 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r2 Banked out Registers Banked out Registers Banked out Registers Banked out Registers Banked out Registers Banked out Registers r3 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 User User User User User FIQ FIQ FIQ FIQ FIQ FIQ IRQ IRQ IRQ IRQ IRQ IRQ SVC SVC SVC SVC SVC SVC Undef Undef Undef Undef Undef Undef Abort Abort Abort Abort Abort Abort r6 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) cpsr cpsr cpsr cpsr cpsr cpsr cpsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr The ARM Register Set

  27. r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr Register Organization Summary User FIQ IRQ SVC Undef Abort Usermoder0-r7,r15,andcpsr Usermoder0-r12,r15,andcpsr Usermoder0-r12,r15,andcpsr Usermoder0-r12,r15,andcpsr Usermoder0-r12,r15,andcpsr Thumb state Low registers r8 r9 Thumb state High registers r10 r11 r12 r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr spsr spsr spsr spsr Note: System mode uses the User mode register set

  28. The Registers • ARM has 37 registers all of which are 32-bits long. • 1 dedicated program counter • 1 dedicated current program status register • 5 dedicated saved program status registers • 30 general purpose registers • The current processor mode governs which of several banks is accessible. Each mode can access • a particular set of r0-r12 registers • a particular r13 (the stack pointer, sp) and r14 (the link register,lr) • the program counter,r15 (pc) • the current program status register, cpsr Privileged modes (except System) can also access • a particular spsr (saved program status register)

  29. Condition code flags N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation oVerflowed Sticky Overflow flag - Q flag Architecture 5TE/J only Indicates if saturation has occurred J bit Architecture 5TEJ only J = 1: Processor in Jazelle state Interrupt Disable bits. I = 1: Disables the IRQ. F = 1: Disables the FIQ. T Bit Architecture xT only T = 0: Processor in ARM state T = 1: Processor in Thumb state Mode bits Specify the processor mode 31 28 27 24 23 16 15 8 7 6 5 4 0 N Z C V Q I F T mode U n d e f i n e d J f s x c Program Status Registers

  30. Program Counter (r15) • When the processor is executing in ARM state: • All instructions are 32 bits wide • All instructions must be word aligned • Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned). • When the processor is executing in Thumb state: • All instructions are 16 bits wide • All instructions must be halfword aligned • Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned). • When the processor is executing in Jazelle state: • All instructions are 8 bits wide • Processor performs a word access to read 4 instructions at once

  31. 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 Exception Handling • When an exception occurs, the ARM: • Copies CPSR into SPSR_<mode> • Sets appropriate CPSR bits • Change to ARM state • Change to exception mode • Disable interrupts (if appropriate) • Stores the return address in LR_<mode> • Sets PC to vector address • To return, exception handler needs to: • Restore CPSR from SPSR_<mode> • Restore PC from LR_<mode> This can only be done in ARM state. FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset Vector Table Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices

  32. Tiva™ TM4C123G Series Overview

  33. Reference material

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