Command & Data Handling System (C&DH) David McGrogan Space Sciences Laboratory

1. Command & Data Handling System (C&DH) David McGrogan Space Sciences Laboratory University of California, Berkeley

2. C&DH Agenda AGENDA Overview CPU Requirements CPU Hardware Reset Behavior Data Flow/Storage Command Upload/Storage Issues

3. Overview SD Card Main Processor Peripherals

4. Requirements

5. CPU Microchip dsPIC33FJ256GP710 16-bit CPU 2 SPI channels (5 Mbps max) 2 UARTs (1 Mbps max) 2 I2C channels (0.4 Mbps max) 2 ECAN channels (can’t really use these) 10s of other pins (timers, ADCs, interrupts, GPIO) 30KB SRAM Useful Features Watchdog timer Brown-out reset Power-saving modes Language Support C compiler, simulator, other items are free SALVO Real-Time Operating System (unused)

6. Reset/Initialization Hardware Reset • Power-On • Watchdog Reset • Ground Command Reset Sequence • Initializes Local Data RAM to zero • Issues Initialization calls to each Module • Starts in Safe Mode (low power) • Begins Engineering Telemetry (1-sec) • Checksums available programs • Selects first program with good checksum • Waits 10 seconds • Runs selected program

7. PIC – Helium xcvr. (UART) PIC – EPS ( I2C ) PIC – SD card (SPI) PIC – FPGA (SPI) Data Paths SD CARD FPGA – Tx (bitstream) FPGA – STEIN (CDI) FPGA – MAGIC (SPI) • Peak Data Flow • Tx : 1 Mbps continuous • SDCARD : 1-2 Mbps average (including RTOS) • STEIN: 16 bits/event, 80KHz events = 1.28Mbps • MAGIC: 19 bits x 20 Hz x 3 axes = .0011 Mbps • Helium 100: 0.0096 Mbps

8. Data Movement Pipelined data flow • For high-volume data flow (STEIN and Tx) • Begin STEIN data import to DMA (512B DMA block) • Immediately begin SD card data export from DMA • Data transfer completes at maximum speed • Requires a block of DMA (512B of 2KB available on chip) Standard buffering • For smaller volumes of data (MAGIC) • Read data explicitly without DMA, store in RAM • Write to SD card when buffer sufficiently filled

9. Solid State Storage • 2 GB SD card • Holds 4.5x the amount downloadable in one pass • Blocks from 1 to 512 bytes possible • Using 512 byte blocks to minimize overhead, increase expandability (SDHC only allows 512B) • Multiple independent circular buffers for engineering, MAGIC, and STEIN data; STEIN buffer is at least half the space (>=500M 16-bit events) Eng. MAGIC STEIN

10. Command uploading and storage • 1200 Bps link through Helium • 4-byte UART FIFO would need handling at 300 Hz • 75 bytes of DMA needed for 16 Hz handling • Uploaded commands are moved to non-DMA circular buffer and handled in order • Commands execute ASAP or at a given future time (expressed in relative time)

11. Issues • Warm-restart possibility – preserve local time and data across undesired resets, execute commands on time (most dsPIC registers are unaffected by a reset) • 200 mW MB draw is over ~100 mW requirement • Power-saving dsPIC modes available, may be irrelevant • Memory allocations (especially 2K DMA area) • Uploading multiple programs – machine code requires some effort to move in program memory (e.g. direct jumps, interrupt pointers)

13. Direct Memory Access (DMA) STEIN COMM 2KB

14. SPI

15. FSW Requirements

16. FSW Requirements