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A small PDA

A small PDA. EEE/CSE 517 project Qinghui Tang, Minghao Cui,. Overview. A small ‘ PDA ’ with some basic and simple functions. Such products can be very helpful in our daily life to work like a clock, a alarm, notepad and e-book. We ’ d like to call it E-pal. System Functions.

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A small PDA

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  1. A small PDA EEE/CSE 517 project Qinghui Tang, Minghao Cui,

  2. Overview • A small ‘PDA’ with some basic and simple functions. • Such products can be very helpful in our daily life to work like a clock, a alarm, notepad and e-book. • We’d like to call it E-pal

  3. System Functions • Display Month, Day and Year • Display Hour and minute • Alarm clock • E-book management: read books, delete books, download books • Set time and alarm time

  4. Parallel port E-book ctrl TimeClock RAM Main control Keyboard Display Notepad ctrl DISP CONTROLL System Diagram

  5. System Memory System Parameters Menu item strings Book memory Note memory Memory Space

  6. Implementation Process • Define System Specification & Function • Behavior and function simulation • Data-flow level simulation • Gate-level simulation • Post-simualtions • Floorplanning

  7. First step : behavior simulation

  8. FSM and diagram

  9. Critical Data Path

  10. RTL level simulation 325ns

  11. Gate-level simulation 325.01ns

  12. Tcl PDA Simulator • Purpose: • to verify system function instead of real hardware implementation(FGPA, CPLD) • TCL scripts • Watch Value of Verilog interl signals • Modify or set Value of Verilog interl signals • Friendly GUI

  13. Test Environment

  14. Floorplanning consideration • Shorten wire length • Decrease routing density • Modules have closed relations put together • External interface

  15. Floorplanning

  16. Gate level module choice • Time_mux • Most other modules is control module, consisted by several Finite State Machines, which is easy to be described by behaviour langugage, but difficult to express with gate-level • Timu_MUX has used basic gates , such as mux, latch. Realize the module into gate-level would give me strong concepts and experience on gate-level circuit.

  17. Questions & Answers

  18. Alarmer

  19. Timer

  20. Time_mux

  21. RTL-level 385ns

  22. Gate-level 385.002ns

  23. Read Verilog Value:Highlight menuitems (1) • GetVariableValueDisplay Memory/mem_bank($addr) • To read hierarchical signal • GetVariableValueDisplay $selection

  24. Read Verilog Value:Highlight menuitems (2)

  25. Stimulus Example run 20 ns force down_arrow 1 run 10 ns force down_arrow 0 run 30 ns

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