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Embedded System Course

Embedded System Course. The Assignments. Hristo Nikolov. Leiden Embedded Research Center Leiden Institute of Advanced Computer Science Leiden University, The Netherlands. Outline. Computer Vision System Overview Edge Detection Image Processing Sobel Edge Detector Application

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Embedded System Course

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  1. Embedded System Course The Assignments Hristo Nikolov Leiden Embedded Research Center Leiden Institute of Advanced Computer Science Leiden University, The Netherlands

  2. Outline • Computer Vision System Overview • Edge Detection Image Processing • Sobel Edge Detector Application • About the Assignments

  3. Computer Vision System Target 1 Target 2 • Computer vision systems are used in the fields of automatic inspection; robotic vision; medical, satellite (and many other) image analyses, etc… • Components: • - Input Image sensor; • - Hardware components; • - Software components. • An Example: Low Speed Obstacle Detection Application - this application is able to detect and to track other vehicles in front of a car in traffic. + = +

  4. Computer Vision System, cntd. • Low level Image Processing: • Content independent processing; • One and the same computations of each pixel; • Edge detection; • Segmentation of the image; • Hundreds calculations per pixel. • High Level Image Processing: • Content dependent processing; • Pattern recognition; • Create a model of the visual scene; • Make a decision what action has to be taken; • Thousands/million calculations per pixel/object.

  5. Why Edge Detection? • Edge detection extracts important features of the image; • Reduces the amount of data that has to be analyzed. • If less data has to be analyzed, more complex algorithms can be applied; • If more complex algorithms are applied, more robust computer vision system can be built. Tens of times less amount of data 57 982 400 p ~2x109calc/sec 1024x768, 3(RGB), 25F/s 56.25MB/sec Input Low level High level

  6. How the information is reduced • The pixel values of the binary image contains only ‘0’ and ‘1’. • The input image contains 270 270 pixels (R,G,B); • Apply an edge detection algorithm; • Apply a threshold – a binary image is created; The resulting binary image has only 4 216 pixels to be analyzed. The amount of data to be processed is reduced 64 times.

  7. Edge Detection edge x (y) Jx(y) * x (y) Convolution mask P3 P6 P1 P2 P4 P5 P7 P8 P10 P9 P12 P11 Convolution(P15) = P8C1 + P9C2+ P10C3+ P14C4 + P15C5 + P16C6 +P20C7 +P21C8 + P22C9 C3 C1 C2 P15 P18 P13 P14 P16 P17 C6 C4 C5 P21 P24 P19 P20 P22 P23 C9 C7 C8 P30 P24 P25 P27 P29 P26 • Locates sharp changes (edges) in the intensity function (image). • Edges are pixels where brightness changes significantly. • The edge detection calculates the gradient at each pixel of the image. • The gradient is calculated as differences in a local neighborhood (3x3) of each pixel using convolution operation.

  8. Sobel Edge Detector 1 -1 -1 -1 -2 0 0 2 -2 0 0 0 1 1 1 -1 0 2 Sobel proposed coefficients of the convolution masks that find Jx and Jy of a local neighborhood of 3x3 pixels: Coefficients of the convolution mask for Jx Coefficients of the convolution mask for Jy

  9. How to apply Sobel Edge Detector For each pixel Pi,j of the input image: • Calculate the gradient components: • Calculate the value of Jxi,j; • Calculate the value of Jyi,j; • Take the absolute values of Jxi,j and Jyi,j; • Gradient Ji,j at pixel Pi,j is equal to the sum of Jxi,j and Jyi,j; • Normalize the result: • Values of the pixels in the input image are within the range 0-255; • The result has to be within the same range.

  10. About the Assignments The assignments contain 3 main parts: • Software (C) implementation of Sobel edge detector; • From C to hardware specification – KPNGen and ESPAM tools; • Hardware implementation on an FPGA prototyping board.

  11. The ESPAM Design Flow Application KPNGen System-Level Specification Mapping Spec in XML KPN in XML Platform Spec in XML Library IP cores Auxiliary files IP cores in VHDL Platform topology description C/C++ code for processors RTL-Level Specification Xilinx Platform Studio (XPS) Tool IP Core Crossbar Executable IP Processor 1 VirtexII-Pro FPGA Gate-Level Specification Executable IP Processor n • Automated parallelization of media/streaming applications into parallel specifications (KPN) • Simple descriptions in XML format • Automated System-to-RTL Level conversion and software code generation ESPAM Tool • Ready for direct implementation • FPGA-based prototyping with ADM-XPL board

  12. ESPAM Demo A B C D E UART Ext Mem Ext Mem MB 1 MB 2 MB 3 MB 4 Crossbar Communication Component Sobel Edge Detection in C KPNGen ESPAM

  13. LeidenUniversity, The Netherlands

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