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1. Microstrip Coupled VCOs for 40-GHz and 43-GHz OC-768 Optical TransmissionDerek K. Shaeffer, Ph.D.Steffen Kudszus, Ph.D.
2. 2 Outline Introduction to Jitter in SONET Systems
Review of Oscillator Phase Noise Theory
VCO Architectural Considerations
Simulation Results
Experimental Results
Summary & Acknowledgments
3. 3 SONET OC-768 optical systems
40 Gb/s (43 Gb/s with FEC)
Serial data
VSR, 2km distances
Timebase challenges
Data jitter
VCO phase noise
Data-dependent jitter (DDJ)
Duty-cycle errors (half-rate systems)
Spec requires less than 2.5ps p-p @ 10-12 BER
That’s 14 standard deviations!
Introduction
4. 4 Integrated Optical Transponder
5. 5 Jitter in SONET Regenerators Two constraints on jitter
“High-Band”: Jitter above the clock recovery bandwidth must be limited to prevent RX data sampling errors
“Wide-Band”: Jitter above the cleanup PLL bandwidth must be limited to prevent FIFO data buffer overflow
6. 6 Jitter Measurement in SONET Systems Timing jitter is recovered from the transmit data stream
Clock recovery loop eliminates jitter below its loop BW
Lowpass filter eliminates high frequency components
Jitter must not exceed specified peak-to-peak values over a 60-second measurement interval
OC-768 Systems (following ITU G.8251)
“Wide-Band”
f1=20 kHz, f2=320 MHz, Jp-p=1.2 UI (30 ps)
“High-Band”
f1=16 MHz, f2=320 MHz, Jp-p=0.1 UI (2.5 ps)
7. 7 Relationship Between Jitter and Phase Noise Given an oscillator with a 1/Df2 phase noise power spectrum, and a measurement system clock recovery bandwidth f1:
Following G.8251, if the oscillator contributes 25% of the jitter power budget, we have two phase noise requirements
Wide-Band: -96 dBc / Hz @ 1-MHz offset
High-Band: -89 dBc / Hz @ 1-MHz offset
8. 8 Review of Oscillator Phase Noise Theory Oscillators exhibit periodic moments of increased phase sensitivity to noise
Characterized by a time-varying impulse response:
Ideally, resonator energy loss is refreshed during moments of low phase sensitivity when G is small
9. 9 Phase Noise of Coupled Oscillators With two coupled oscillators (N=2)
Impulse sensitivity reduced by 6 dB
Double the number of noise sources
Net improvement is 3dB
No better than spending twice the power
Generally, improvement is 10*log10(N)
However, additional improvement beyond 3dB can be gained if coupling leads to better refresh pulse alignment
10. 10 A Prototype Pulsed Oscillator Colepitts oscillator generates refresh pulses coinciding with “good” moments of the resonator oscillation
Applying Hajimiri phase noise theory to collector shot noise…
11. 11 Minimizing Oscillator Jitter Minimize GRMS
Optimize the timing of refresh pulses
Use coupled, pulsed oscillators for this purpose
Maximize resonator quality factor (Q)
Careful selection of resonator type
Use high-Q tuning elements, particularly varactors
Spend the necessary current
12. 12 Effect of Loop Delay on Pulse Timing Reduction of loop gain and startup margin
Off-resonance oscillation and reduction of oscillation amplitude
Mistiming of refresh pulse
13. 13 Delay Compensation Using Coupled Oscillators Refresh pulse timing is corrected by:
The oscillator operates on-resonance if M is set properly
14. 14 Simulated Oscillation Waveforms
15. 15 Resonator Types Spiral
Substrate eddy losses
Challenge to model & optimize
Susceptible to noise injection by magnetic coupling
Coplanar Waveguide
Good shorted line
Need two vias at the open end
Shielded variety has Low L/um
Unshielded variety is more susceptible to noise injection
Microstripline
Good open line
Need one via at each end
Higher L/um (Q ~ 20 @ 40GHz)
Easy to model and scale
16. 16 Resonator Considerations Shorted microstrip transmission line resonator
Advantages
Predictable with 2-D or 3-D field solvers
Compact layout
Immunity to substrate noise coupling (electric and magnetic)
Scalability
Reasonable quality factor (Q ~15)
Disadvantage
Via losses at shorted end can significantly degrade Q
MOS accumulation mode varactor
Advantage
Highest quality factor for a given capacitance adjustment range (Q~30)
Disadvantage
Steep tuning slope
17. 17 Microstripline Test Measurements 2.5mm test line
4-mm thick Al over an M1/M2 shield
Fit RLC simulation model at 40-GHz
Q ~ 15
Loss ~ 0.56 dB/mm
18. 18 Resonator Architecture Virtual ground at nodes X and Y replaces shorting via
Active circuitry can be positioned at both ends in very close proximity to the lines
Resistive elements damp out all but one oscillation mode
19. 19 Circuit Architecture Colepitts-like pulsed operation
Capacitive coupling network sets the coupling coefficient independent of pulse network parasitics
20. 20 Quadrature VCO Block Diagram Two resonators, cross-coupled to produce in-phase and quadrature oscillations.
For testing, only brought out the in-phase signal.
21. 21 Simulated Phase Noise Performance
22. 22 Experimental Prototype Implemented 40-GHz and 43-GHz oscillators
Die area is 0.189 mm2 for 40-GHz version
120-GHz fT SiGe BiCMOS process
Packaged in a custom ceramic package w/ V-connectors
Phase noise measurements taken on battery power w/ Vtune terminated to GND
23. 23 Tuning Characteristics
24. 24 Measured Phase Noise Performance
25. 25 Performance Summary
26. 26 Epilogue – VCO in action in 4:1 MUX / CMU(ISSCC 2003 Paper 13.4, JSSC Dec 2003)
27. 27 20-GHz Clock Distribution Used on-chip transmission lines
Common-base receivers terminate line and isolate load
Can drive long line lengths with only modest current
28. 28 VCO Tuning Range
29. 29 CMU Phase Noise Measurements Jitter meets specifications with ~ 7 dB margin
Jitter could be further reduced by 1.8 dB by optimizing CMU bandwidth
Optimum CMU bandwidth ~ 15 MHz
30. 30 40 Gb/s Eye Diagram (231-1 PRBS) Used Agilent 86107A precision timebase and 83484A 50-GHz plug-in
Timebase jitter ~150fs, RMS
CMU random jitter generation (total) ~ 125fs, RMS
Data patterning jitter ~ 3ps, pk-pk
31. 31 50 Gb/s Eye Diagram (Probed) Wafer probed through 3-ft of semi-rigid cable.
Scope has about 1ps, RMS jitter
Eye closure mostly due to cabling
Small amount of eye asymmetry
32. 32 Summary and Acknowledgments Demonstrated 40-GHz and 43-GHz VCOs
Both meet or exceed requirements for SONET OC-768
Coupled oscillator architecture improves phase noise by about 11dB without additional power consumption
Dual microstrip resonator eliminates via losses and minimizes layout parasitics
20-GHz versions applied in OC-768 transponder product
Acknowledgments
This work was performed at Big Bear Networks, Inc.
Steffen Kudszus collaborated in this work
Carlos Bowen for layout assistance
Yuheng Lee for help with test package assembly
Tad Labrie for testing assistance