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Lecturer PSOE Dan Garcia cs.berkeley/~ddgarcia

Understand the design of a single-cycle CPU datapath using Verilog, including memory implementation, register transfers, and control logic. Step-by-step guide on analyzing instruction requirements and developing the datapath.

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Lecturer PSOE Dan Garcia cs.berkeley/~ddgarcia

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  1. inst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures Lecture 33 – Single Cycle CPU Datapath, with Verilog II2004-04-14 Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia Google Gmail Service!! Not so fast! State Sen Liz Figueroa (Fremont) is drafting legislation to block it because it’d place advertising in personal messages after searching them for keywords. “We think it's an absolute invasion of privacy. It's like having a massive billboard in the middle of your home.”

  2. Storage Element: Idealized Memory Write Enable Address • Memory (idealized) • One input bus: Data In • One output bus: Data Out • Memory word is selected by: • Address selects the word to put on Data Out • Write Enable = 1: address selects the memoryword to be written via the Data In bus • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • Address valid => Data Out valid after “access time.” Data In DataOut 32 32 Clk

  3. Verilog Memory for MIPS Interpreter (1/3) //Behavioral modelof Random Access Memory: // 32-bit wide, 256 words deep, // asynchronous read-port if RD=1, // synchronous write-port if WR=1, // initialize from hex file ("data.dat") // on positive edge of reset signal, // dump to binary file ("dump.dat") // on positive edge of dump signal. module mem (CLK,RST,DMP,WR,RD,address,writeD,readD); input CLK, RST, DMP, WR, RD; input [31:0] address, writeD; output [31:0] readD; reg [31:0] readD; parameter memSize=256; reg [31:0] memArray [0:memSize-1]; integer chann,i; // ~ Constant dec. // Temp variables: for loops...

  4. Verilog Memory for MIPS Interpreter (2/3) integer chann,i; always @ (posedge RST) $readmemh("data.dat", memArray); always @ (posedge CLK) if (WR) memArray[address[9:2]] = writeD; always @ (address or RD) if (RD) begin readD = memArray[address[9:2]]; $display("Getting address %h containing %h", address[9:2], readD); end // write if WR & positive clock edge (synchronous) // read if RD, independent of clock (asynchronous)

  5. Why is it “memArray[address[9:2]]”? • Our memory is always byte-addressed • We can lb from 0x0, 0x1, 0x2, 0x3, … • lw only reads word-aligned requests • We only call lw with 0x0, 0x4, 0x8, 0xC, … • I.e., the last two bits are always 0 • memArray is a word wide and 28 deep • reg [31:0] memArray [0:256-1]; • Size = 4 Bytes/row * 256 rows = 1024 B • If we’re simulating lw/sw, we R/W words • What bits select the first 256 words? [9:2]! • 1st word = 0x0 = 0b000 = memArray[0]; 2nd word = 0x4 = 0b100 = memArray[1], etc.

  6. Verilog Memory for MIPS Interpreter (3/3) end; always @ (posedge DMP) begin chann = $fopen("dump.dat"); if (chann==0) begin $display("$fopen of dump.dat failed."); $finish; end for (i=0; i<memSize; i=i+1) begin $fdisplay(chann, "%b", memArray[i]); end end // always @ (posedge DMP) endmodule // mem // Temp variables chan, i

  7. Peer Instruction • We should use the main ALU to compute PC=PC+4 • We’re going to be able to read 2 registers and write a 3rd in 1 cycle • Datapath is hard, Control is easy ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

  8. How to Design a Processor: step-by-step • 1. Analyze instruction set architecture (ISA) => datapath requirements • meaning of each instruction is given by the register transfers • datapath must include storage element for ISA registers • datapath must support each register transfer • 2. Select set of datapath components and establish clocking methodology • 3. Assemble datapath meeting requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic (hard part!)

  9. Storage Element: Register (Building Block) Write Enable • Register • Similar to the D Flip Flop except • N-bit input and output • Write Enable input • Write Enable: • negated (or deasserted) (0): Data Out will not change • asserted (1): Data Out will become Data In Data In Data Out N N Clk

  10. Verilog 32-bit Register for MIPS Interpreter // Behavioral model of 32-bit Register: // positive edge-triggered, // synchronous active-high reset. module reg32 (CLK,Q,D,RST); input [31:0] D; input CLK, RST; output [31:0] Q; reg [31:0] Q; always @ (posedge CLK) if (RST) Q = 0; else Q = D; endmodule // reg32

  11. Storage Element: Register File RW RA RB • Register File consists of 32 registers: • Two 32-bit output busses: busA and busB • One 32-bit input bus: busW • Register is selected by: • RA (number) selects the register to put on busA (data) • RB (number) selects the register to put on busB (data) • RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1 • Clock input (CLK) • The CLK input is a factor ONLY during write operation • During read operation, behaves as a combinational logic block: • RA or RB valid => busA or busB valid after “access time.” Write Enable 5 5 5 busA busW 32 32 32-bit Registers 32 busB Clk 32

  12. Verilog Register File for MIPS Interpreter (1/3) // Behavioral model of register file: // 32-bit wide, 32 words deep, // two asynchronous read-ports, // one synchronous write-port. // Dump register file contents to // console on pos edge of dump signal.

  13. Verilog Register File for MIPS Interpreter (2/3) module regFile (CLK, wEnb, DMP, writeReg, writeD, readReg1, readD1, readReg2, readD2); input CLK, wEnb, DMP; input [4:0] writeReg, readReg1, readReg2; input [31:0] writeD; output [31:0] readD1, readD2; reg [31:0] readD1, readD2; reg [31:0] array [0:31]; reg dirty1, dirty2; integer i; • 3 5-bit fields to select registers: 1 write register, 2 read register

  14. Verilog Register File for MIPS Interpreter (3/3) always @ (posedge CLK) if (wEnb) if (writeReg!=4'h0) // why? begin array[writeReg] = writeD; dirty1=1'b1; dirty2=1'b1; end always @ (readReg1 or dirty1) begin readD1 = array[readReg1]; dirty1=0; end

  15. Step 3: Assemble DataPath meeting requirements • Register Transfer Requirements Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation

  16. Next Address Logic Address Instruction Memory 3a: Overview of the Instruction Fetch Unit • The common RTL operations • Fetch the Instruction: mem[PC] • Update the program counter: • Sequential Code: PC = PC + 4 • Branch and Jump: PC = “something else” Clk PC Instruction Word 32

  17. 3b: Add & Subtract • R[rd] = R[rs] op R[rt] Ex.: addU rd, rs, rt • Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields • ALUctr and RegWr: control logic after decoding the instruction 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 • Already defined register file, ALU

  18. . . . . . . . . . . . . Clocking Methodology Clk • Storage elements clocked by same edge • Being physical devices, flip-flops (FF) and combinational logic have some delays • Gates: delay from input change to output change • Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF, and we have the usual clock-to-Q delay • “Critical path” (longest path through logic) determines length of clock period

  19. Register-Register Timing: One complete cycle Clk New Value Old Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value RegWr Old Value New Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value Rd Rs Rt ALUctr Register Write Occurs Here RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32

  20. 11 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits rd? 31 16 15 0 immediate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 bits 16 bits Rd Rt RegDst Mux 3c: Logical Operations with Immediate • R[rt] = R[rs] op ZeroExt[imm16] ] What about Rt register read?? Rt? Rs ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 Mux ZeroExt imm16 32 16 ALUSrc • Already defined 32-bit MUX; Zero Ext?

  21. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3d: Load Operations • R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 Rd Rt RegDst Mux Rt? Rs ALUctr RegWr 5 5 5 busA W_Src Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk MemWr 32 Mux Mux WrEn Adr Data In 32 ?? Data Memory Extender 32 imm16 32 16 Clk ALUSrc ExtOp

  22. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3e: Store Operations • Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 Rd Rt ALUctr MemWr W_Src RegDst Mux Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers ALU 32 32 busB Clk Mux 32 Mux WrEn Adr Data In 32 32 Data Memory imm16 Extender 32 16 Clk ALUSrc ExtOp

  23. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 3f: The Branch Instruction • beq rs, rt, imm16 • mem[PC]Fetch the instruction from memory • Equal = R[rs] == R[rt] Calculate the branch condition • if (Equal) Calculate the next instruction’s address • PC = PC + 4 + ( SignExt(imm16) x 4 ) else • PC = PC + 4

  24. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 4 Adder Mux PC Adder Clk Datapath for Branch Operations • beq rs, rt, imm16 Datapath generates condition (equal) Inst Address Cond nPC_sel Rs Rt RegWr 5 5 5 busA 32 Rw Ra Rb 00 busW 32 32 32-bit Registers Equal? busB Clk 32 imm16 PC Ext • Already MUX, adder, sign extend, zero

  25. Inst Memory Adr Adder Mux Adder Putting it All Together:A Single Cycle Datapath Instruction<31:0> <0:15> <21:25> <16:20> <11:15> Rs Rt Rd Imm16 RegDst nPC_sel ALUctr MemWr MemtoReg Equal Rt Rd 0 1 Rs Rt 4 RegWr 5 5 5 busA Rw Ra Rb = 00 busW 32 32 32-bit Registers ALU 0 32 busB 32 0 PC 32 Mux Mux Clk 32 WrEn Adr 1 1 Data In Data Memory imm16 Extender 32 PC Ext Clk 16 imm16 Clk ExtOp ALUSrc

  26. Peer Instruction Suppose we’re writing a MIPS interpreter in Verilog. Which sequence below is best organization for the interpreter? • repeat loop that fetches instructions • while loop that fetches instructions • Decodes instructions using case statement • Decodes instr. using chained if statements • Executes each instruction • Increments PC by 4 1: ACEF 2: ADEF 3: AECF 4: AEDF 5: BCEF 6: BDEF 7: BECF 8: BEDF 9: EF 0: FAE

  27. PC ALU Clk An Abstract View of the Implementation Control Ideal Instruction Memory Control Signals Conditions Instruction Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out 32 Rw Ra Rb 32 Ideal Data Memory 32 32 32-bit Registers Next Address Data In B Clk Clk 32 Datapath

  28. Summary: Single cycle datapath • 5 steps to design a processor • 1. Analyze instruction set => datapath requirements • 2. Select set of datapath components & establish clock methodology • 3. Assemble datapath meeting the requirements • 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. • 5. Assemble the control logic • Control is the hard part • Next time! Processor Input Control Memory Datapath Output

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