Computer Architecture and Design – ECEN 350

Computer Architecture and Design – ECEN 350 Part 1 – Introduction Dr. G. Choi Dept. of Electrical and Computer Engineering [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson, P. Gratz, and others]

Instructor Information: • Dr. Gwan S. Choi • Office 333G WERC • Office Hours: • TBA (tentative)(or by appointment) • http://www.ece.tamu.edu/~gchoi/main.html • Email: gwanchoi@gmail.com

TA Information: • Ehsan Rohani • Office 332A WERC • Office Hours: • T 11- 12; R 10-11 (tentative) (or by appointment) • http://people.tamu.edu/~ehsanrohani/ • Email: ehsanohani@neo.tamu.edu

Required textbook: • Computer Organization and Design: The Hardware/Software Interface by Patterson and Hennessy. Morgan Kaufmann publishers, 4th Edition, Revised Printing, Morgan Kaufmann 2008 • Other editions can be used as well

Reference textbook: • M. Ciletti. Starter's Guide to Verilog 2001

Course info • Mailing list: • Emails will be sent periodically to your TAMU email account • Announcements: • Lecture cancellations • Deadline extension • Updates, etc. • Course information • Some course information can be found at: http://people.tamu.edu/~ehsanrohani/ • Syllabus, Lab assignments, HW assignments, lecture slides etc.

Course description • Computer architecture and design • Use of register transfer languages and simulation tools to describe and simulate computer operation • Central processing unit organization, • Microprogramming; • Input/output; • Memory system architectures.

Attention over time! t

Attention over time! ~5 min t

Labs • 5Assembly language labs • Using SPIM simulator • 6Hardware design labs • Verilog – Xilinx Webpack • Can run from your home PC, using PCSPIM and Xilinx software.

Labs • First week’s lab covers orientation/procedures • No recitation the first week • No lab this Tuesday week

Assignments • Assignments will be assigned most weeks. • The purpose of the assignments is to prepare you for the midterm and the final exam.

Grading scale • A standard grading scale will be utilized. • A90-100% • B 80-89% • C 70-79% • D 60-69% • F Below 59% Full syllabus will be available on course website

Course Goals • Address topics such as • What is a computer? • How to program a computer? • Assembly language programming • How to build a computer? • Verilog-based hardware design and verification

Course Goals Auxiliary Goals Main Goals

Course Goals • Understand hardware architecture • Learn design methodology • Learn very general tools for the design of sophisticated digital systems

ECEN 350 Computer organization Application (ex: browser) • Coordination of many levels (layers) of abstraction Operating Compiler System (Mac OSX) Software Assembler Instruction Set Architecture Hardware Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors

Levels of Representation High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,MIPS) Assembler Machine Language Program (MIPS) Machine Interpretation Hardware Architecture Description (Logic, Logisim, etc.) Architecture Implementation Logic Circuit Description (Logisim, etc.)

Levels of Representation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,MIPS) Assembler Machine Language Program (MIPS) Machine Interpretation Hardware Architecture Description (Logic, Logisim, etc.) Architecture Implementation Logic Circuit Description (Logisim, etc.)

Levels of Representation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,MIPS) Assembler Machine Language Program (MIPS) Machine Interpretation Hardware Architecture Description (Logic, Logisim, etc.) Architecture Implementation Logic Circuit Description (Logisim, etc.)

Levels of Representation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,MIPS) Assembler 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Machine Language Program (MIPS) Machine Interpretation Hardware Architecture Description (Logic, Logisim, etc.) Architecture Implementation Logic Circuit Description (Logisim, etc.)

Anatomy: Components of any Computer Keyboard, Mouse Computer Processor Memory (where programs, data live when running) Devices Disk(where programs, data live when not running) Input Control (“brain”) Datapath (“brawn”) Output Display, Printer

Content • MIPS instruction set • Principles of computer architecture: • CPU datapath and control unit design • ALU Design • Pipelined Datapath • Memory hierarchies and design • I/O organization and design

Topics • Introduction • Computer organization • Moore’s law • Performance modeling • Impact of advancing technology • Operation of the computer hardware

Topics • Instruction Set Architectures (ISA) • Representing instructions on the computer • Arithmetical and logical instructions • Memory access instructions • Control flow instructions • Function calls instructions • Input-output instructions • SPIM- instruction set simulator

Topics • Computer Arithmetic • Signed and unsigned numbers • Addition and subtraction • Multiplication • Division • Floating point operations

Topics • Translating and starting a program • Compilers, compiler optimization • Object code generation, assemblers • Linking • Run-time execution environment

Topics • Performance evaluation • CPU performance and its factors • Performance metrics • Performance factors • Comparing performance • SPEC benchmarks

Topics • Hardware Description Languages (HDL) • Verilog hardware description language • Design-Simulation Process • Structural Designs in Verilog • Behavioral HDL Description of Systems

Topics • Datapathand Control (5) • ALU design • Single-cycle implementation • Multi-cycle implementation • Microprogramming

Topics • Pipelining (5) • Pipelined datapath • Pipelined control • Pipeline hazards: structural, control, data • Hazard detection and resolution • Exception handling

Topics • Memory Hierarchy • Overview of SRAM and DRAM design • Basic of caches • Framework for memory hierarchy • Measuring memory performance • Peripherals • Disk storage and dependability • I/O devices and their interface to the processor • Buses and other connections

SPIM Assembler and Simulator • SPIM is a self-contained assembler and simulator for the MIPS32 assembly language programs • Provides a simple assembler, debugger and a simple set of operating system services • Implements both a simple, terminal-style interface and a visual windowing interface

SPIM Assembler and Simulator • Available as • xspim on unix,linux, and Mac OS X • PCSpimon Windows • QtSpim on both (we’ll use QtSpim in the lab) • can be downloaded and installed on your own PC from www.cs.wisc.edu/~larus/spim.html

Xilinx WebPack and ModelSim • Allow users to enter digital logic designs, as either schematic or HDL, and simulate them. • Xilinx ISE WebPACK, which includes Project Navigator, is used for design entry • ModelSim is used for simulation • Available from • http://www.xilinx.com/tools/webpack.htm

What you should already know • How to write, compile and run programs in a higher level language (C, C++, Java, …) • In this course we will use C as a high-level language • How to represent and operate on positive and negative numbers in binary form (two’s complement, sign magnitude, etc.)

Sample program float pow(floatx, uint exp) { float result=1.0; inti; for (i=0; (i < exp); i++) { result = result * x; } return result; } intmain(intargc, char **argv) { float p; p = pow(10.0, 5); printf(“p = %f\n”, p); return 0; }

Sample C program fragment /* define an array of 10 chars */ char x[5] = {‘t’,’e’,’s’,’t’,’\0’}; /* accessing element 0 */ x[0] = ‘T’; /* pointer arithmetic to get elt 3 */ char elt3 = *(x+3); /* x[3] */ /* x[0] evaluates to the first element; * x evaluates to the address of the * first element, or &(x[0]) */ /* 0-indexed for loop idiom */ #define COUNT 10 char y[COUNT]; inti; for (i=0; i<COUNT; i++) { /* process y[i] */ printf(“%c\n”, y[i]); }

What you should already know • Logic design (ECEN 248) • Design of combinatorial and sequential components • Boolean algebra • logic minimization • decoders and multiplexors, latches and flip-flops, registers, • Mealy/Moore finite state machines, etc.

The Underlying Technologies

The PowerPC • Introduced in 1999 • 3.65M transistors • 366 MHz clock rate • 40 mm2 die size • 250nm technology

Intel Pentium 4 • Introduced in 2004 • 125M transistors • 3.8 GHz clock • 122 mm2 die • 90nm tech 4

Intel “Gulftown” i7 • Introduced in 2010 • 1.17 billion transistors • 3.3 GHz clock • 248 mm2 die • 32 nm tech • 6 cores/12 threads

Technology Trends: Microprocessor Complexity # of transistors on an IC • 2X Transistors / Chip • Every 1.5 years • Called • “Moore’s Law” Year

Growth in processor performance

Clock rate and power

DRAM Capacity

Impacts of Advancing Technology • Processor • logic capacity: increases about 30% per year • performance: 2x every 1.5 years (slowing!) 100x performance in last decade • Memory • DRAM capacity: 4x every 3 years, about 60% per year • memory speed: 1.5x every 10 years • cost per bit: decreases about 25% per year • Disk • capacity: increases about 60% per year

Computer Technology - Dramatic Change! Impacts of Advancing Technology State-of-the-art PC when you graduate: Processor clock speed: 5000 MegaHertz (5.0 GigaHertz) Memory capacity: 8000 MegaBytes (8.0 GigaBytes) Disk capacity: 2000 GigaBytes (2.0 TeraBytes) New units! Mega => Giga, Giga => Tera(Tera=> Peta, Peta => Exa, Exa => ZettaZetta => Yotta = 1024)

Computer Architecture and Design – ECEN 350