1 / 5

Migration to PPC at JLab

Migration to PPC at JLab. Richard Dickson. VME data interface differences:. mvme177. System Local Bus. 68060 CPU. VMEchip2. VME. mvme2700. System Local Bus. PPC 750 CPU. PCI Bus. Raven. Universe. VME.

quyn-case
Download Presentation

Migration to PPC at JLab

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Migration to PPC at JLab Richard Dickson

  2. VME data interface differences: mvme177 System Local Bus 68060 CPU VMEchip2 VME mvme2700 System Local Bus PPC 750 CPU PCI Bus Raven Universe VME • The completely different bridge chips’ register set resulted in low level VME Direct Memory Access (DMA) code having to be rewritten. • Any hard coded system local bus mapped VME addresses fail on this migration since PPC VxWorks maps VME blocks to different space.

  3. VME interrupt differences: • Only even VME interrupt vectors allowed. • VME interrupt does not preempt ongoing DMA. ISR ISR DMA transfer Time IRQ IRQ • “Bad VME interrupt 0” messages on console. • move stop_irq_value, EOI_reg ; write does not complete before • rfi ; return from interrupt • In this case the code execution can erroneously exit interrupt context prior to the IRQ being de-asserted. This was fixed partially by executing an “Enforce In-order Execution of IO (eieio)” instruction prior to the rfi.

  4. Other Problems: • VxWorks for the mv2700 configures the PowerPC floating point unit to issue an exception on divide by zero faults (causing task suspension). This was not the case for the 162, 167, 177. The VxWorks taskSpawn command was overloaded to issue a call to this assembly language code to disable FP exceptions on behalf of the task being spawned. • In pursuit of increased performance, the PowerPC CPU will combine two consecutive sequential 16 bit writes into a single 32 bit write (referred to as Store Gathering). address 16 Bit address 32 Bit address + 2 16 Bit

  5. Other Problems (cont.): • Non-volatile RAM used for maintaining IOC reboot/save/restore dates is not directly accessible (memory mapped) as is the case for a 162, 167, 177 board. Custom driver code was written to emulate this functionality on the 2700. • A custom, low level code package (known as timevt) existed to provide asynchronous short period timer functionality. This utilized 162/167/177 specific hardware timer architecture that is unavailable on the 2700 platform. • The CAMAC interface driver did not work. • Serial applications need to be tested. • cmlog had problems building.

More Related