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CS 152 Computer Architecture and Engineering Lecture 10 Multicycle Controller Design (Continued)

CS 152 Computer Architecture and Engineering Lecture 10 Multicycle Controller Design (Continued) . October 3, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/. Equal. Partitioning the CPI=1 Datapath.

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CS 152 Computer Architecture and Engineering Lecture 10 Multicycle Controller Design (Continued)

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  1. CS 152 Computer Architecture and EngineeringLecture 10Multicycle Controller Design (Continued) October 3, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/ ©UCB Fall 2001

  2. Equal Partitioning the CPI=1 Datapath • Add registers between smallest steps • Place enables on all registers MemWr MemWr MemRd RegWr RegDst nPC_sel ALUSrc ExtOp ALUctr Reg. File Exec Operand Fetch Instruction Fetch Mem Access PC Next PC Result Store Data Mem ©UCB Fall 2001

  3. MemToReg RegWr RegDst MemRd MemWr ALUctr ALUSrc ExtOp Reg. File Ext ALU S Mem Access M Data Mem Result Store Recap: Example Multicycle Datapath • Critical Path ? Equal nPC_sel E Reg File A PC IR Next PC B Instruction Fetch Operand Fetch ©UCB Fall 2001

  4. Execute Memory Write-back Recap: FSM specification “instruction fetch” IR <= MEM[PC] 0000 “decode” A <= R[rs] B <= R[rt] 0001 LW R-type ORi SW BEQ PC <= Next(PC) S <= A fun B S <= A or ZX S <= A + SX S <= A + SX 0100 0110 1000 1011 0011 M <= MEM[S] MEM[S] <= B PC <= PC + 4 1001 1100 R[rd] <= S PC <= PC + 4 R[rt] <= S PC <= PC + 4 R[rt] <= M PC <= PC + 4 0101 0111 1010 ©UCB Fall 2001

  5. Types of “branching” • Set state to 0 • Dispatch (state 1) • Use incremented state number 1 State Reg Adder Address Select Logic Sequencer-based control unit: Statemachine ++ Control Logic Multicycle Datapath Outputs Inputs Opcode ©UCB Fall 2001

  6. Recap: Micro-controller Design • The state digrams that arise define the controller for an instruction set processor are highly structured • Use this structure to construct a simple “microsequencer” • Each state in previous diagram becomes a “microinstruction” • Microinstructions often taken sequentially • Control reduces to programming this device sequencer control datapath control microinstruction () micro-PC sequencer ©UCB Fall 2001

  7. Recap: Specific Sequencer from last lecture • Sequencer-based control unit from last lecture • Called “microPC” or “µPC” vs. state register Control Value Effect00 Next µaddress = 0 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1 ROM: 1 microPC Adder R-type 000000 0100 BEQ 000100 0011 ori 001101 0110 LW 100011 1000 SW 101011 1011 Mux 2 1 0 0 µAddress Select Logic ROM Opcode ©UCB Fall 2001

  8. Recap: Microprogram Control Specification µPC Taken Next IR PC Ops Exec Mem Write-Back en sel A B Ex Sr ALU S R W M M-R Wr Dst 0000 ? inc 1 0001 0 load 0001 1 inc 0010 x zero 1 1 0011 x zero 1 0 0100 x inc 0 1 fun 1 0101 x zero 1 0 0 1 1 0110 x inc 0 0 or 1 0111 x zero 1 0 0 1 0 1000 x inc 1 0 add 1 1001 x inc 1 0 1 1010 x zero 1 0 1 1 0 1011 x inc 1 0 add 1 1100 x zero 1 0 0 1 BEQ R: ORi: LW: SW: ©UCB Fall 2001

  9. Recap: Overview of Control • Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation PLA ROM Technique “hardwired control” “microprogrammed control” ©UCB Fall 2001

  10. Processor Input Control Memory Datapath Output The Big Picture: Where are We Now? • The Five Classic Components of a Computer • Today’s Topics: • Microprogramed control • Administrivia • Microprogram it yourself • Exceptions ©UCB Fall 2001

  11. Microprogramming (Maurice Wilkes) • Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance ©UCB Fall 2001

  12. “Macroinstruction” Interpretation User program plus Data this can change! Main Memory ADD SUB AND . . . one of these is mapped into one of these DATA execution unit AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) CPU control memory ©UCB Fall 2001

  13. Variations on Microprogramming ° “Horizontal” Microcode – control field for each control point in the machine ° “Vertical” Microcode – compact microinstruction format for each class of microoperation – local decode to generate all control points (remember ALU?) branch: µseq-op µadd execute: ALU-op A,B,R memory: mem-op S, D µseq µaddr A-mux B-mux bus enables register enables Horizontal Vertical ©UCB Fall 2001

  14. Extreme Horizontal 3 1 input select . . . N3 N2 N1 N0 1 bit for each loadable register enbMAR enbAC . . . Incr PC ALU control Depending on bus organization, many potential control combinations simply wrong, i.e., implies transfers that can never happen at the same time. Makes sense to encode fields to save ROM space Example: mem_to_reg and ALU_to_reg should never happen simultaneously; => encode in single bit which is decoded rather than two separate bits NOTE:the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction ©UCB Fall 2001

  15. More Vertical Format next states inputs src dst other control fields MUX D E C D E C Some of these may have nothing to do with registers! Multiformat Microcode: 6 1 3 Branch Jump 0 cond next address 1 3 3 3 1 dst src alu Register Xfer Operation D E C D E C ©UCB Fall 2001

  16. Hybrid Control Not all critical control information is derived from control logic E.g., Instruction Register (IR) contains useful control information, such as register sources, destinations, opcodes, etc. enable signals from control Register File R S 1 D E C R S 2 D E C R D D E C rs1 IR op rs2 rd to control ©UCB Fall 2001

  17. Vax Microinstructions VAX Microarchitecture: 96 bit control store, 30 fields, 4096 µinstructions for VAX ISA encodes concurrently executable "microoperations" 95 87 84 68 65 63 11 0 USHF UALU USUB UJMP 001 = left 010 = right . . . 101 = left3 010 = A-B-1 100 = A+B+1 00 = Nop 01 = CALL 10 = RTN Jump Address ALU Control Subroutine Control ALU Shifter Control Current intel architecture: 80-bit microcode, 8192 instructions ©UCB Fall 2001

  18. Horizontal vs. Vertical Microprogramming NOTE: previous organization is not TRUE horizontal microprogramming; register decoders give flavor of encoded microoperations Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Vertical + easier to program, not very different from programming a RISC machine in assembly language - extra level of decoding may slow the machine down Horizontal + more control over the potential parallelism of operations in the datapath - uses up lots of control store ©UCB Fall 2001

  19. Administration • Midterm on Wednesday (10/10) from 5:30 - 8:30 in 277 Cory Hall • No class on that day • Pizza and Refreshments afterwards at LaVal’s on Euclid • I’ll Buy the pizza • LaVal’s has an interesting history • Review Session: • Sunday (10/7), 7:00 PM in 306 Soda???? • Material through this Friday • Look over Lab 4 soon! • Must email breakdown to your TA by Friday night at midnight ©UCB Fall 2001

  20. How Effectively are we utilizing our hardware? IR <- Mem[PC] • Example: memory is used twice, at different times • Ave mem access per inst = 1 + Flw + Fsw ~ 1.3 • if CPI is 4.8, imem utilization = 1/4.8, dmem =0.3/4.8 • We could reduce HW without hurting performance • extra control A <- R[rs]; B<– R[rt] S <– A + B S <– A or ZX S <– A + SX S <– A + SX M <– Mem[S] Mem[S] <- B R[rd] <– S; PC <– PC+4; R[rt] <– S; PC <– PC+4; R[rd] <– M; PC <– PC+4; PC <– PC+4; PC < PC+4; PC < PC+SX; ©UCB Fall 2001

  21. “Princeton” Organization A-Bus B Bus • Single memory for instruction and data access • memory utilization -> 1.3/4.8 • Sometimes, muxes replaced with tri-state buses • Difference often depends on whether buses are internal to chip (muxes) or external (tri-state) • In this case our state diagram does not change • several additional control signals • must ensure each bus is only driven by one source on each cycle A Reg File next PC P C IR S Mem B ZX SX W-Bus ©UCB Fall 2001

  22. 32 0 Mux 0 Mux 1 Instruction Reg 32 ALU Out 0 1 Mux 32 32 1 ALU Control Mux 1 0 << 2 Extend 16 Today: Alternative datapath (book) PCWr PCWrCond PCSrc • Miminizes Hardware: 1 memory, 1 adder Zero ALUSelA IorD MemWr IRWr RegDst RegWr 1 Mux 32 PC 0 Zero 32 Rs Ra 32 RAdr 5 32 Rt 32 Rb busA A ALU Ideal Memory 32 Reg File 5 4 Rt 0 Rw 32 WrAdr 32 B 1 32 Rd Mem Data Reg Din Dout busW busB 2 32 3 Imm 32 ALUOp ExtOp MemtoReg ALUSelB ©UCB Fall 2001

  23. New Finite State Machine (FSM) Spec IR <= MEM[PC] PC <= PC + 4 “instruction fetch” 0000 “decode” Q: How improve to do something in state 0001? 0001 LW BEQ R-type ORi SW ALUout <= A fun B ALUout <= A or ZX ALUout <= A + SX ALUout <= A + SX ALUout <= PC +SX Execute 0100 0110 1000 1011 0010 M <= MEM[ALUout] MEM[ALUout] <= B Memory If A = B then PC <= ALUout 1001 1100 0011 R[rd] <= ALUout R[rt] <= ALUout R[rt] <= M Write-back 0101 0111 1010 ©UCB Fall 2001

  24. Finite State Machine (FSM) Spec IR <= MEM[PC] PC <= PC + 4 “instruction fetch” 0000 ALUout <= PC +SX “decode” 0001 LW BEQ R-type ORi SW ALUout <= A fun B ALUout <= A or ZX ALUout <= A + SX ALUout <= A + SX If A = B then PC <= ALUout Execute 0100 0110 1000 1011 0010 M <= MEM[ALUout] MEM[ALUout] <= B Memory 1001 1100 R[rd] <= ALUout R[rt] <= ALUout R[rt] <= M Write-back 0101 0111 1010 ©UCB Fall 2001

  25. Designing a Microinstruction Set 1) Start with list of control signals 2) Group signals together that make sense (vs. random): called “fields” 3) Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last) 4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals • Use computers to design computers 5) To minimize the width, encode operations that will never be used at the same time ©UCB Fall 2001

  26. 1&2) Start with list of control signals, grouped into fields Signal name Effect when deasserted Effect when assertedALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs]RegWrite None Reg. is written MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rdMemRead None Memory at address is read, MDR <= Mem[addr]MemWrite None Memory at address is written IorD Memory address = PC Memory address = SIRWrite None IR <= MemoryPCWrite None PC <= PCSourcePCWriteCond None IF ALUzero then PC <= PCSourcePCSource PCSource = ALU PCSource = ALUoutExtOp Zero Extended Sign Extended Single Bit Control Signal name Value EffectALUOp 00 ALU adds 01 ALU subtracts 10 ALU does function code 11 ALU does logical OR ALUSelB 00 2nd ALU input = 4 01 2nd ALU input = Reg[rt] 10 2nd ALU input = extended,shift left 2 11 2nd ALU input = extended Multiple Bit Control ©UCB Fall 2001

  27. Start with list of control signals, cont’d • For next state function (next microinstruction address), use Sequencer-based control unit from last lecture • Called “microPC” or “µPC” vs. state register Signal Value EffectSequen 00 Next µaddress = 0 -cing 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1 • Could even include “branch” option which changes microPC by adding offset when certain control signals are true. 1 microPC Adder Mux 2 1 0 0 µAddress Select Logic ROM Opcode ©UCB Fall 2001

  28. 3) Microinstruction Format: unencoded vs. encoded fields Field Name Width Control Signals Set wide narrow ALU Control 4 2 ALUOp SRC1 2 1 ALUSelA SRC2 5 3 ALUSelB, ExtOp ALU Destination 3 2 RegWrite, MemtoReg, RegDst Memory 3 2 MemRead, MemWrite, IorD Memory Register 1 1 IRWrite PCWrite Control 3 2 PCWrite, PCWriteCond, PCSource Sequencing 3 2 AddrCtl Total width 24 15 bits ©UCB Fall 2001

  29. 4) Legend of Fields and Symbolic Names Field Name Values for Field Function of Field with Specific ValueALU Add ALU adds Subt. ALU subtracts Func code ALU does function code Or ALU does logical ORSRC1 PC 1st ALU input = PC rs 1st ALU input = Reg[rs]SRC2 4 2nd ALU input = 4 Extend 2nd ALU input = sign ext. IR[15-0] Extend0 2nd ALU input = zero ext. IR[15-0] Extshft 2nd ALU input = sign ex., sl IR[15-0] rt 2nd ALU input = Reg[rt]destination rd ALU Reg[rd] = ALUout rt ALU Reg[rt] = ALUout rt Mem Reg[rt] = Mem Memory Read PC Read memory using PC Read ALU Read memory using ALUout for addr Write ALU Write memory using ALUout for addrMemory register IR IR = MemPC write ALU PC = ALU ALUoutCond IF ALU Zero then PC = ALUoutSequencing Seq Go to sequential µinstruction Fetch Go to the first microinstruction Dispatch Dispatch using ROM. ©UCB Fall 2001

  30. Quick check: what do these fieldnames mean? Destination: CodeName RegWrite MemToReg RegDest 00 --- 0 X X 01 rd ALU 1 0 1 10 rt ALU 1 0 0 11 rt MEM 1 1 0 SRC2: Code Name ALUSelB ExtOp 000 --- X X 001 4 00 X 010 rt 01 X 011 ExtShft 10 1 100 Extend 11 1 111 Extend0 11 0 ©UCB Fall 2001

  31. 32 0 Mux 0 Mux 1 Instruction Reg 32 ALU Out 0 1 Mux 32 32 1 ALU Control Mux 1 0 << 2 Extend 16 Alternative datapath (book): Multiple Cycle Datapath PCWr PCWrCond PCSrc • Miminizes Hardware: 1 memory, 1 adder Zero ALUSelA IorD MemWr IRWr RegDst RegWr 1 Mux 32 PC 0 Zero 32 Rs Ra 32 RAdr 5 32 Rt 32 Rb busA A ALU Ideal Memory 32 Reg File 5 4 Rt 0 Rw 32 WrAdr 32 B 1 32 Rd Mem Data Reg Din Dout busW busB 2 32 3 Imm 32 ALUOp ExtOp MemtoReg ALUSelB ©UCB Fall 2001

  32. Microprogram it yourself! Label ALU SRC1 SRC2 ALU Dest. Memory Mem. Reg. PC Write Sequencing Fetch: Add PC 4 Read PC IR ALU Seq ©UCB Fall 2001

  33. Microprogram it yourself! Label ALU SRC1 SRC2 Dest. Memory Mem. Reg. PC Write Sequencing Fetch: Add PC 4 Read PC IR ALU Seq Add PC Extshft Dispatch Rtype: Func rs rt Seq rd ALU Fetch Ori: Or rs Extend0 Seq rt ALU Fetch Lw: Add rs Extend Seq Read ALU Seq rt MEM Fetch Sw: Add rs Extend Seq Write ALU Fetch Beq: Subt. rs rt ALUoutCond. Fetch ©UCB Fall 2001

  34. Legacy Software and Microprogramming • IBM bet company on 360 Instruction Set Architecture (ISA): single instruction set for many classes of machines • (8-bit to 64-bit) • Stewart Tucker stuck with job of what to do about software compatibility • If microprogramming could easily do same instruction set on many different microarchitectures, then why couldn’t multiple microprograms do multiple instruction sets on the same microarchitecture? • Coined term “emulation”: instruction set interpreter in microcode for non-native instruction set • Very successful: in early years of IBM 360 it was hard to know whether old instruction set or new instruction set was more frequently used ©UCB Fall 2001

  35. Microprogramming Pros and Cons • Ease of design • Flexibility • Easy to adapt to changes in organization, timing, technology • Can make changes late in design cycle, or even in the field • Can implement very powerful instruction sets (just more control memory) • Generality • Can implement multiple instruction sets on same machine. • Can tailor instruction set to application. • Compatibility • Many organizations, same instruction set • Costly to implement • Slow ©UCB Fall 2001

  36. An Alternative MultiCycle DataPath A-Bus • In each clock cycle, each Bus can be used to transfer from one source • µ-instruction can simply contain B-Bus and W-Dst fields B Bus A Reg File next PC P C inst mem IR mem S B ZX SX W-Bus ©UCB Fall 2001

  37. What about a 2-Bus Microarchitecture (datapath)? Instruction Fetch A-Bus B Bus A Reg File next PC P C IR S Mem M B ZX SX Decode / Operand Fetch A Reg File next PC P C IR S Mem M B ZX SX ©UCB Fall 2001

  38. Load Execute • What about 1 bus ? 1 adder? 1 Register port? A Reg File next PC P C IR S Mem M B ZX SX Mem addr A Reg File next PC P C IR S Mem M B ZX SX Write-back A Reg File next PC P C IR S Mem M B ZX SX ©UCB Fall 2001

  39. Summary • Specialize state-diagrams easily captured by microsequencer • simple increment & “branch” fields • datapath control fields • Most microprogramming-based controllers vary between: • horizontal organization (1 control bit per control point) • vertical organization (fields encoded in the control memory and must be decoded to control something) • Steps: • identify control signals, group them, develop “mini language”, then microprogram • Control design reduces to Microprogramming • Arbitrarily complicated instructions possible ©UCB Fall 2001

  40. Summary: Microprogramming one inspiration for RISC • If simple instruction could execute at very high clock rate… • If you could even write compilers to produce microinstructions… • If most programs use simple instructions and addressing modes… • If microcode is kept in RAM instead of ROM so as to fix bugs … • If same memory used for control memory could be used instead as cache for “macroinstructions”… • Then why not skip instruction interpretation by a microprogram and simply compile directly into lowest language of machine? ©UCB Fall 2001

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