Input/Output Systems

1. Input/Output Systems

2. Why I/O is important • How to control a motor using a PC? • The motor will be regarded as an output device • How can the computer communicate with the motor?

3. I/O using ADuC832 ADuC832 PORT Display

4. Introduction • The I/O (Input/Output) interface permits the microprocessor to communicate with the outside world, eg to control an external device • How can you connect a keyboard, or a mouse, to a 8086 or P6 microprocessor? • The 8086 microprocessor can only access external components (including memory devices) via the address and data buses

5. Concept of I/O • The mechanism is similar to the memory interface because the CPU is using the same set of buses – data and address • Data transfer still takes place over the multiplexed address/data bus

6. I/O and Memory interface

7. Minimum-mode interface • To connect to external I/O devices, usually some interface circuits are required • Interface circuitry is used to bridge the microprocessor and the I/O (Input/Output) devices • Functions of the interface – select the I/O port (decoding), latch output data, adjust the signal levels etc • Only address/data lines from 0-15 are used for interfacing with external I/O devices

8. Block diagram for IO system The control signals are same as those used in memory operations

9. I/O address space • The interface between the CPU and an external device is called an I/O Port (just like the Ports in 89C51, or ADuC832) but there is NO physical I/O port provided by the 8086 • I/O ports is similar to address locations. • When an I/O device is connected to a CPU the device will occupy an I/O port • An I/O port is similar to an address in memory (i.e each Port has an unique number) Each port can support 8-bit data • If an external device requires 16-bit data then it will occupy two ports

10. I/O Ports • I/O Port addresses (16-bit) (or Port numbers ) are generated by the microprocessor via the ADn lines and after proper decoding, correct I/O port can be selected • AD16 to AD19 are held at 0 for I/O operations • M/IO signal is set to 0 to indicate I/O operations (this is the only different between read/write of an I/O and memory)

11. I/O ports for a PC

12. WindowsXP system I/O information

13. I/O instructions • How to read/write to/from I/O devices? • In 8086, IN and OUT are I/O instructions • IN - input from port into AL or AX • OUT - Output from AL or AX to port • IN AL, FF (move a byte in from port FF) • OUT FF, AL (move a byte out from AL to port FF) • IN and OUT are called direct instruction to access I/O ports

14. I/O instructions • Using IN, or OUT in direct instruction the max. port no. is 255 (FF) • How to access Ports from 256-FFFFH?

15. I/O instructions • Can also use indirect with DX holding the port address • IN AL, DX • OUT DX, AL • Indirect addressing can access 64K ports (WHY?)

16. Example Data are to be read in from two byte-wide input ports at address AA and A9, respectively, and then output as a word to a word-wide Output port at address B000. Write a sequence of instructions to Perform this I/O operation IN AL, AA ; move data in from port address AA MOV AH,AL ; move data from AL to AH IN AL,A9 ; move data from port address A9 MOV DX, B000 ; move port address B000 to DX OUT DX, AX ; can I do OUT B000, AX instead ?????? AH AL Data from AA Data from A9

17. I/O bus cycles • READ Cycle – same as for memory operation • M/IO – set to 0 to identify I/O operation • /DEN – switch to 0 to signal the I/O interface circuitry when to put data onto the bus. DEN – Device ENable • Write cycle – data available in the bus in T2 and maintained during the rest of the bus cycle • /WR – switches to logic 0 to signal that valid data are on the bus

18. I/O read cycle

19. I/O Write cycle

20. I/O interface • To interface with I/O devices an interface circuit is needed • Usually also requires a decoding mechanism • The diagram in the next slide shows a simple circuit to interface with 64 1-bit I/O devices (or 8 8-bit I/O devices) • Each device will occupy an I/O port number

21. 64 Output lines (8 ports) circuit I/O 8282 – Octal latch Decoder

22. Example • Refer to the previous diagram • To which port are data being written when the address put on the bus during an output bus cycle is 8002(Hex) • How to output the byte contents of the memory location called DATA to output Port 0 by simple assembly language?

23. The input select for the 8205 is driven by A1 A2 and A3 For the address 8002, the 3 bits are 001 So Port 1 is selected The control required to select the Port 0 is 8000 (refer to above, Port 1 is 8002) The instruction is Mov DX, 8000 Mov AL, DATA Out DX, AL

24. 8255A Programmable Peripheral Interface (PPI) • It is an LSI peripheral designed to permit easy implementation of parallel I/O in the PC systems. It provides a flexible parallel interface, such as input and output ports; level-sensitive inputs; latched outputs; strobed inputs or outputs; and strobed bidirectional input/outputs. These features are selected under software control. 8255 can interface any TTL-compatible I/O device to the microprocessor. • 8255 is used to interface keyboard and parallel printer port

26. Block diagram of 8255PPI To/From I/O devices To/From CPU

27. 8255 PPI • It consists of 3 ports • Each port is 8-bit • Address A0 and A1 (these are input of 8255 not 8086) are used to select the port to read/write • Data are transferred through an 8-bit bidirectional data bus • Chip select (/CS) of the 8255 must be enabled

28. Register-Select Code • The microprocessor must apply this code to the register-select inputs A0 and A1 of the 8255A.

29. 8255 PPI • An 8255 PPI will occupy at least 4 I/O addresses (Port A to C and the control) • The A1A0 of the 8255 usually connected to address lines of the CPU. Therefore, changing the 0, 1 of the lines can provide different port numbers

30. 8255 decoding If Port A is 1238H and Port B is 123AH Can you identify which Two address lines are Connected to A1A0? Decoder Address 8255 8086 /CS A1 A0

31. Example • If PortA occupies location 1238H and PortB occupies 123AH, can you determine addresses occupied by other Ports? What address lines are connected to A1A0 of the 8255? • According to the previous table A1A0 is • Port A = 00 (address 1238H 1000 digit 8 ) • Port B = 01 ( address 123AH 1010 digit A) • Which two lines are the most likely answer? • Can you identify the Port numbers for the other two ports?

32. Example Determine Ports Occupied By the 8255 3x8 multiplexer

33. To/From I/O devices To/From CPU Data – connect to data bus /RD – connect to /RD of the uP (active when reading data from 8255) /WR – connect to /WR of the uP (active when writing data to 8255) /CS – connect to decoding device (active when reading or writing to or from 8255)

34. Control of the 8255 • Before you can make use of the 8255, you must configure (or program) the device • The control of the 8255 is via the programming of the internal control register • The register is represented by (or divided into) group A and group B control blocks • Input/Output operations are controlled by different bit-patterns

35. 8255 PPI • To program the 8255, A1A0 = 11 and a write cycle is initialized so that the proper bit pattern is written to the control register • After the configuration then the PORTs A, B, C can be used accordingly

36. Control Word bit functions

37. Control Bits • D0 – set input/output for lower 4-bit of Port C (1 for input; 0 for output ) • D1 – set input/output for 8-bit of Port B • D2 – mode selection (0 – mode 0; 1 – mode 1) • D3 – same as D0 but for upper 4-bit • D4 – same as D1 but for Port A • D6 & D5 – mode selection (00 – mode 0, 01 –mode 1, 1X – mode 2) • D7 – mode set flag ( 1- active)

38. Mode Selection • Mode set flag is the D7 bit in the control, it must be at logic 1 whenever the mode operation is to be changed. • There are three modes of operation which are known as mode 0, mode 1, and mode 2 respectively. • We will only discuss Mode 0 and Mode 1!!!! • But you should study Mode 2 by yourself!!!!!!!

39. Mode control of 8255 Example: If control register is at Port 20H How to configure the 8255 to work with Port A Mode 0 inputand Port B and C mode 0 output ?

40. Mode 0 – simple I/O • Mode 0 selects what is called simple I/O operation, i.e., the lines of the port can be configured as level-sensitive inputs or latched output. • Output ports are latched. Input ports are not latched???? • Output ports are latched – data remain in the output port until you perform another output operation • This is very similar to the Ports provided by the ADuC832 (the microprocessor used in the lab.)

41. Example What is the mode and I/O configuration for ports A, B, and C of an 8255A after its control register is loaded with 82Hex The binary pattern is 10000010 (82H) refer to the table of control word D0 = 0 lower 4 bits of Port C are outputs D1 = 1 Port B are inputs D2 = 0 mode 0 operation for both Port B and the lower 4 bits of Port C D3 = 0 upper 4 bits of Port C are outputs D4 = 0 Port A are outputs D6D5 = 00 mode 0 operation for both Port A and the upper part Of Port C D7 =1 mode enable

42. Mode 0 • Output port is latched so data remain available until the next write operation • Input port no latch so when data is available then the device must read otherwise the data can be lost because there is no buffer (latch) to store the incoming data

43. Mode 1 – Strobed I/O • Mode 1 represents what is known as strobed I/O. In this mode, the A and B ports are configured as two independent byte-wide I/O ports, each of which has a 4-bit control/data port associated with it. The control/data ports are formed from the lower and upper 4-bit of port C respectively. • Both input and output are latched • Data applied to an input port must be strobed-inwith a signal produced by an external hardware

44. Mode 1 –Strobe I/O • In computing, the term handshake usually refers to steps that need to follow in order to complete a task • Handshake signal is provided for a port when in mode 1 • Handshake represents the available of data, or when an external device has read these data

45. An analogy of 8255 in Mode 1 input CPU 8255 Device The above diagram shows the relationship between CPU, 8255 and external device 8255 is only the middle-man, so after receiving “data”, 8255 must inform the CPU to read the data But since the internal buffer of the 8255 can only store 1 byte of data, therefore, 8255 also signal external device not to write again when data is already inside the buffer The handshake signal is used for such purposes.

46. Mode 1 control pins definition • If Port A is in mode 1 input then • Upper 4-bit of Port C is reconfigured to provide the Port A • Control/data lines • PCx – PC (Port C bit x ) • PC4 – strobe input (/STBA) (to strobe data in Port A into the latch) • (1 -> 0) high -> low • PC5 – input buffer full when 1 (IBFA) this is an output to signal external device) • PC3 – interrupt request (INTRA) (used when action should be performed by the microprocessor ) (output) • PC6,7 – I/O (can use to input/output 2 bits of information

47. What is strobe-in? Data Strobe signal In order to put data into a latch There is usually a control signal (the strobe) The signal must be activated (1->0) so that Data in the input side will be stored inside the Latch Similar to ALE !!!!!!!!!!!!!!!! Latch

48. Mode 1 operation Input Data come from external device STBA – issued by external device to latch data into 8255 buffer 8255 issues INTRA IBFA to signal CPU to read data INTE A – interrupt enable if this bit is set then the INTRA will be issued

49. Strobe input Strobed input (mode 1) causes port A and/or port B to function as latching input devices. External data is stored in the port until the microprocessor is ready to retrieve it by issuing a /RD signal. Strobed input port captures data from the port when the /STB is activated. The /STB signal (1->0) causes data to be captured and it activates the IBF (Input Buffer Full) and INTR (Interrupt Request). IBF (a ‘1’) indicates that data are in port A. Once the microprocessor notices that data are strobed into the port, it executes an IN instruction to read the port.

50. Strobe Input • The act of reading the port restores both IBF and INTR • IBF – reset by the rising edge of /RD input • INTR – reset by a falling edge of /RD