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No Pipeline

No Pipeline. add r3, r1, r2 add r6,r4, r5 add r9, r7, r8 add r12, r10,r11 add r15, r13,r14. time. 1. IF. ID. EX. MEM. WB. IF. ID. EX. MEM. WB. 2. IF. ID. EX. MEM. WB. 3. IF. ID. EX. MEM. WB. 4. Assuming 1 cycle for IF/ID/EX/MEM/WB,

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No Pipeline

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  1. No Pipeline add r3, r1, r2 add r6,r4, r5 add r9, r7, r8 add r12, r10,r11 add r15, r13,r14 time 1 IF ID EX MEM WB IF ID EX MEM WB 2 IF ID EX MEM WB 3 IF ID EX MEM WB 4 Assuming 1 cycle for IF/ID/EX/MEM/WB, Total # cycles for n instructions: n*5 For n = 5 => (25 cycles) instr

  2. 5-stage Pipeline add r3, r1, r2 add r6,r4, r5 add r9, r7, r8 add r12, r10,r11 add r15, r13,r14 time 1 IF ID EX MEM WB IF ID EX MEM WB 2 IF ID EX MEM WB 3 IF ID EX MEM WB 4 IF ID EX MEM WB 5 Assuming 1 cycle for IF/ID/EX/MEM/WB, Total # cycles for n instructions = 5 + (n-1) = n + 4 For (n = 5) => (9 cycles) instr

  3. Pipeline Forwarding add r3, r1, r2 add r5,r4, r3 add r7, r6, r5 add r10, r7,r8 add r12, r10,r9 time 1 IF ID EX MEM WB IF ID EX MEM WB 2 IF ID EX MEM WB 3 Forwarding: To communicate deps between stage of earlier inst to following insts IF ID EX MEM WB 4 IF ID EX MEM WB 5 Assuming 1 cycle for IF/ID/EX/MEM/WB, Total # cycles for n instructions = 5 + (n-1) = n + 4 For (n = 5) => (9 cycles) instr

  4. Superscalar with Issue Width = 2 time add r3, r1, r2 add r6,r4, r5 add r9, r7, r8 add r12, r10,r11 add r15, r13,r14 1 IF ID EX MEM WB IF ID EX MEM WB 2 IF ID EX MEM WB 3 IF ID EX MEM WB 4 IF ID EX MEM WB 5 instr Assuming 1 cycle for IF/ID/EX/MEM/WB, Total # cycles for n instructions = 5 + ceil[(n-2)/2] For (n = 5) => (7 cycles)

  5. SIMD Pipeline Assume 5-element vector v1 = [r1, r4, r7,r10,r13] v2 = [ r2, r5, r8, r11, r14] time 1 IF ID EX MEM WB addv v3, v1, v2 EX Single vector instrtakes 5 cycles (5 scalar insts in 7 cycles on superscalar) EX EX addv v6, v5, v4 addv v9, v8, v7 EX IF ID EX MEM WB 2 (Total of 15 scalar adds in 7 cycles) vs (4 scalar adds in 7 cycles) EX EX IF ID EX MEM WB EX EX instr EX EX Fewer instructions operate on more elements in parallel 3 EX EX EX

  6. What if you had dependencies between vector insts ? addv v3, v1, v2 addv v5, v4, v3 addv v7, v6, v5

  7. Vector SIMD Pipeline: Chaining time 1 IF ID EX MEM WB EX EX EX EX IF ID EX MEM WB 2 EX EX IF ID EX MEM WB Vector SIMD Pipeline (Chaining): Composition of SIMD with Pipeline Forwarding EX EX instr EX EX 3 EX EX EX

  8. Vector SIMD Pipeline: Chaining time 1 IF ID EX MEM WB EX IF ID/EX EX MEM WB IF/EX ID/EX EX MEM WB EX IF/EX ID/EX EX MEM WB 2 EX EX EX EX EX EX EX EX EX EX 3

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