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Learning Outcome

EEE2243 Digital System Design Chapter 2: Verilog HDL (Sequential) by Muhazam Mustapha, February 2012. Learning Outcome. By the end of this chapter, students are expected to be able to: Design State Machine Write Verilog State Machine by Boolean Algebra and by Behavior. Chapter Content.

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Learning Outcome

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  1. EEE2243Digital System DesignChapter 2: Verilog HDL (Sequential)by Muhazam Mustapha, February 2012

  2. Learning Outcome • By the end of this chapter, students are expected to be able to: • Design State Machine • Write Verilog State Machine by Boolean Algebra and by Behavior

  3. Chapter Content • Finite State Machine • Controller Design

  4. Finite State Machine Vahid §3.3 pg 122

  5. Formalism Finite State Machine consists of: A set of states A set of inputs A set of outputs An initial state A set of transitions depending on input conditions An action associated to each state that tells how the output value is computed Finite state machine is used to define sequential circuit behavior Vahid pg 126

  6. Capturing FSM Behavior Design of FSM at gate level (in introductory courses) are tedious because we have to manually design the combinational circuit, minimize the state, condition the flip-flop to change, etc At HDL level (intermediate courses), all those are done by software, and the actual hardware is provided by the FPGA which means in many cases minimization is irrelevant For this chapter, we will do only some minimization mentally

  7. Capturing FSM Behavior Scheme to capture FSM: List states Create transitions Refine FSM: mentally try to figure out if states can be reduce, circuit can be minimized Example and demo: Oscillator Counter design Vahid pg 129

  8. Oscillator clock Q D 1 0 clk On Q Off clock module Osc(Q, clk); input clk; output Q; reg Q; always@(negedge clk) begin Q <= 0; #10; Q <= 1; #10; endendmodule module Osc(Q, clk); input clk; output Q; reg Q; always@(negedge clk) begin Q <= ~Q; #10; endendmodule By Boolean Algebra By behavior Vahid pg 504

  9. Counter • Counter is a sequential circuit that stores the no. times certain events occur – normally the clock pulses • There are a few types of counters, but for our course we will only design synchronous counter with D flip-flop • Counters are characterized by the no. of counts it can store • in term of FSM this is called states • Counters that store N counts (N states) is called mod N counters

  10. Full Counter • Mod N counters with N = 2n (n = no. registers) are called full counters • Full counters use all available states that can be provided by the registers • Just as the combinational circuits, full counters can also be defined in Verilog as Boolean Algebra or behavioral • effectively there is only one way to define the counter by boolean approach – just as the boolean expression that defines it • there are more than one ways to define by behavioral approach

  11. 4-Bit Full Counter Boolean Algebra Style • Defining counters (or any other FSM) as boolean algebra requires calculations involving excitation table:

  12. 4-Bit Full Counter Boolean Algebra Style • We can take the plain excitation equations, or minimize them: AB AB CD CD AB AB CD CD

  13. 4-Bit Full Counter Boolean Algebra Style • The circuit: Q Q Q Q D D D D clk clk clk clk Q Q Q Q D C B A

  14. 4-Bit Full Counter Boolean Algebra Style • The Verilog code: module FC4Bit(c, clk); input c; output [3:0] clk; reg [3:0] clk; always@(negedge c) begin clk[3] <= ~clk[3]; clk[2] <= ~clk[2]&clk[3] | clk[2]&~clk[3]; clk[1] <= clk[1]&~clk[2] | clk[1]&~clk[3] | ~clk[1]&clk[2]&clk[3]; clk[0] <= clk[0]&~clk[1] | clk[0]&~clk[2] | clk[0]&~clk[3] | ~clk[0]&clk[1]&clk[2]&clk[3]; endendmodule

  15. 4-Bit Full Counter Boolean Algebra Style • Or Verilog code with keyword wire to structure your code: module FC4Bit(c, clk); input c; output [3:0] clk; reg [3:0] clk; wire AND1, AND2, AND3; wire AND4, AND5, AND6; wire AND7, AND8, AND9; assign AND1 = ~clk[2]&clk[3]; assign AND2 = clk[2]&~clk[3]; assign AND3 = clk[1]&~clk[2]; assign AND4 = clk[1]&~clk[3]; assign AND5 = ~clk[1]&clk[2]&clk[3]; assign AND6 = clk[0]&~clk[1]; assign AND7 = clk[0]&~clk[2]; assign AND8 = clk[0]&~clk[3]; assign AND9 = ~clk[0]&clk[1]&clk[2]&clk[3]; always@(negedge c)begin clk[3] <= ~clk[3]; clk[2] <= AND1|AND2; clk[1] <= AND3|AND4|AND5; clk[0] <= AND6|AND7|AND8|AND9;endendmodule

  16. 4-Bit Full Counter Behavioral Style • The Verilog code: • Or: module FC4Bit(c, clk); input c; output [3:0] clk; reg [3:0] clk; always@(negedge c) case (clk) 0: clk = 1; 1: clk = 2; 2: clk = 3; 3: clk = 4; 4: clk = 5; 5: clk = 6; 6: clk = 7; 7: clk = 8; 8: clk = 9; 9: clk = 10; 10: clk = 11; 11: clk = 12; 12: clk = 13; 13: clk = 14; 14: clk = 15; 15: clk = 0; endcaseendmodule module FC4Bit(c, clk); input c; output [3:0] clk; reg [3:0] clk; always@(negedge c) clk <= clk+1;endmodule

  17. Partial Counter • Mod N counters with N < 2n (n = no. registers) are called partial counters • Partial counters don’t use all available states that can be provided by the registers • The counting sequence skips some states in order to produce the required counting mod

  18. 3-Bit Partial Counter Behavioral Style • 3-bit mod 5 counter with initial value 2 (keyword initial): module FC4Bit(c, clk); input c; output [2:0] clk; reg [2:0] clk; initial clk <= 2; always@(negedge c) begin if (clk == 6) clk <= 2; else clk <= clk+1; endendmodule • Try on your own the Boolean style to write this counter, as well as other ways to write the behavior code

  19. Controller Design Vahid §3.3 pg 132

  20. Controller A controller is an FSM in form of a counter with certain output produced when it is in a specific state We specify the machine as general construct, then the actual implementation depends on the actual hardware We just specify FSM in a standard architecture FSM inputs O I FSM outputs Combinational logic S m m m-bit state register clk N Vahid pg 132

  21. Controller Steps Vahid pg 133 - modified

  22. Controller Design Discussion w Inputs: none; Outputs: w,x,y,z Inputs: none; Outputs: w,x,y,z x y wxyz=0001 wxyz=1000 wxyz=0001 wxyz=1000 Combinational logic z A D A D n1 00 11 n0 s1 s0 01 10 State register B C B C clk wxyz=0011 wxyz=1100 wxyz=0011 wxyz=1100 Step 2: Create architecture Step 1: Create FSM Step 3: Encode states w FSM outputs x y z n0 n1 s1 s0 State register clk Step 4: Create state table • Want generate sequence 0001, 0011, 1100, 1000, (repeat) • Each value for one clock cycle • Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor” w = s1 x = s1s0’ y = s1’s0 z = s1’ n1 = s1 xor s0 n0 = s0’ a Step 5: Create combinational circuit Vahid slide

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