Today’s Subject

1. Today’s Subject • Continue on some basics on single-wall CNT----chiral length, angle and band gap; • Other properties of CNT; • Device applications; • Growth of CNT; • Si nanowires; • Other nanowires; • Growth Challenges.

2. “Roll” Carbon Nanotube from Graphene 2 Ch = n a1 + m a2(n, m); (n, m are integers; 0  m  n). cos = Ch a1 / |Ch||a1|.

3. Nanotube Chirality

4. Examples of Band Structures 4 One-dimensional energy dispersion relations for (a) armchair (5, 5), (b) zigzag (9, 0), and (c) zigzag (10, 0) carbon nanotubes.

5. Bandgap of Semiconducting Tube 5

6. ATM or STM Used to Determine Chirality (11,7)

7. Multi Wall Tubes Multi-wall CNT TEM Image

8. Material Properties of CNT-continued

9. Comparison of Other Materials to CNT Space Elevator CNT cable Super strong, light weight

10. Material Properties of CNT-continued

11. Electronic Applications CNT transistor

12. Demonstration of CNT Memory Design http://www.nantero.com/index.html • Applied charge make CNT ribbons bend down to touch the substrate or bend up back to its original state. • Ribbon-up gives 'zero' and ribbon-down is 'one'.

13. Structure • Fabricated on a silicon wafer, CNT ribbons are suspended 100 nanometers above a carbon substrate layer.

14. Off-State

15. On-State

16. Read-Out

17. Structural and Mechanical Applications

18. CNT interconnect Lines

19. Bottom-up Approach for CNT interconnects

20. Sensors, NEMS Applications

21. CNT-based Bio Sensors

23. Carbon Nanotube Growth

24. Three Basic CNT Growth Methods C A B A: Laser ablation; B: Arc discharge; C: Catalytic chemical vapor deposition (CCVD). All currently known methods consist of some variant of one of these approaches.

25. Bottom-up Growth of CNTs

26. CNT Nanoelectrode Array

27. Si Nanowires Ultrahigh piezoresistance of Si nanowire: sensor application, actuator, microscope cantilever, etc. A Si nanowire MOSFET

28. Si Nanowire Growth Vapor-Liquid-Solid mechanism Si nanowire growth. Difference between Si nanowire and CNT: CNT is hollow, but Si nanowire is solid with crystalline core.

29. Si Nano Wire Transistors

30. Nanowire-based Vertical Gate Transistor

31. ZnO Nanowires

32. Challenges of Nanowire Growth

33. Challenges of Nanowire Growth

34. Nanoelectronics – Now or Never?" IEDM Evening Panel Discussion, December 14, Session 26: 8:00 p.m. Continental Ballroom 6-9 Moderator: Mark Lundstrom, Purdue University "Nanoelectronics – Now or Never?" Traditional 'top-down' microelectronics has become nanoelectronics with device dimensions comparable to those being explored in the new field of ëbottom-up' nano- and molecular electronics. We use the terms, top-down and bottom-up, in a very general sense. Top-down refers to a way of thinking and building that begins at the macro (continuum) scale and pushes to the nanoscale. Bottom-up refers to a way of thinking and building that begins at the atomistic level and builds up to the nanoscale. The top-down approach has already delivered silicon MOSFETs with channel lengths of ~ 5nm, but scaling down device dimensions with commensurate increase in device and system performance is increasingly challenging. Bottom-up technology has demonstrated molecular switches, nanotube and nanowire FET's, NDR and single electron devices, and ultra-dense memory prototypes. Is bottom-up nanotechnology ready to address the industry's challenges, or is it still long-term research with essentially unpredictable outcomes? This panel will debate the question of what the intersection of top-down and bottom-up electronics will mean to semiconductor technology of the future.