1 / 10

CajunBot Hardware and Software Architecture Overview

This document outlines the hardware and software architecture of CajunBot, including hardware topology, control loop, laser drivers, obstacle detection, path planning, robot controller, and data flow management. It discusses shared memory, interprocess communication, code structure, and resolving concurrency conflicts in a distributed system. Key topics include process topology scaling, distributing shared memory queues using NDDS middleware, and addressing architectural concerns such as tuning queue sizes, managing process priorities, optimizing shared memory usage, and employing real-time operating systems.

randler
Download Presentation

CajunBot Hardware and Software Architecture Overview

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CajunBot: Hardware and Software Architecture

  2. Hardware Topology

  3. CajunBot Control Loop

  4. Laser Drivers Steering Module Obstacle Detection Path Planning Robot Controller Drivers PosMV Drivers 3-D terrain of obstacles Path to follow Commands controlling device Raw sensor data Formatted sensor data Data Flow Architecture

  5. Code Code Code Private Data Private Data Private Data Shared Data Shared Data Shared Data Interprocess Communication • POSIX Shared Memory

  6. Resolving Concurrency Conflicts • Queues in shared memory • Circular • Pre-allocated • No dynamic allocation • Single writer per queue • Multiple readers

  7. Process Topology

  8. Scaling Computation • Shared memory • Tied to a single computer • May have multiple processors • Replace motherboard with better processor, more memory • Limited growth • Alternative • Distribute Shared Memory

  9. Code Code Code Code Code Code Private Data Private Data Private Data Private Data Private Data Private Data Shared Data Shared Data Shared Data Shared Data Shared Data Shared Data Distributing Shared Memory Queues • NDDS – Publish/Subscribe middleware NDDS Middleware

  10. Architectural Issues • Tuning the size of the queues? • Managing the priority of processes? • Optimizing shared memory use? • Using real-time OS

More Related