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班級：積體所碩一 學生：林欣緯 指導教授：林志明 教授

A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation M. Mansuri et al. , “ A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation ” IEEE J. Solid-State Circuits, vol. 38, No. 11, November 2003. 班級：積體所碩一 學生：林欣緯 指導教授：林志明 教授. Outline.

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班級：積體所碩一 學生：林欣緯 指導教授：林志明 教授

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  1. A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise CompensationM. Mansuri et al., “A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation” IEEE J. Solid-State Circuits, vol. 38, No. 11, November 2003 班級：積體所碩一 學生：林欣緯 指導教授：林志明 教授

  2. Outline • Introduction • PLL architecture • Measurement Results • Performance Comparison • Reference

  3. PLL block diagram

  4. Jitter definition • PLL易受電源電壓變動及晶片基板雜訊(Substrate noise)干擾而產生Jitter， • Jitter是指一個週期波形變動量Δt • Jitter可分為cycle to cycle Jitter及absolute Jitter

  5. PLL architecture

  6. PFD architecture PFD輸出有三種型態， (Up,Down)分別為 (1,0)、(0,1)、(0,0)。 Up&Down均為零時 表示PLL為相鎖狀態。

  7. Loop filter architecture

  8. VCO with noise-canceling circuit

  9. Quadrature pseudo-differential CCO circuit

  10. Compensated inverter

  11. PLL and clock bufferingdie photograph

  12. Measured and simulated VCO gain

  13. PLL output jitter histogram at 1 GHz

  14. Measurement Results

  15. Performance Comparison

  16. Reference • M. Mansuri et al., “A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation” IEEE J. Solid-State Circuits, vol. 38, No. 11, November 2003

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