1 / 32

ALTERA UP2 Tutorial 1: The 15 Minute Design

ALTERA UP2 Tutorial 1: The 15 Minute Design. ALTERA UP2 Tutorial 1: The 15 Minute Design. Figure 1.1 The Altera UP 1 CPLD development board. ALTERA UP2 Tutorial 1: The 15 Minute Design. Design. Compilation. Simulation. Verifcation. Graphical Entry. Timing Diagram. Program CPLD.

raquel
Download Presentation

ALTERA UP2 Tutorial 1: The 15 Minute Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ALTERA UP2Tutorial 1: The 15 Minute Design

  2. ALTERA UP2Tutorial 1: The 15 Minute Design Figure 1.1 The Altera UP 1 CPLD development board.

  3. ALTERA UP2Tutorial 1: The 15 Minute Design Design Compilation Simulation Verifcation GraphicalEntry Timing Diagram Program CPLD Compiler Timing Analysis UP 1 Development Board HDLEntry Figure 1.2 Design process for schematic or VHDL entry.

  4. Figures 2.1 The Altera UP 2 board.

  5. Figures 2.1 The Altera UP 2 board.

  6. Table 2.1 UP 2 device selection jumpers for programming.

  7. Figure 2.3 MAX and FLEX seven-segment LED display segment names.

  8. Table 2.4 UP 2 Board 10K20RC240 FLEX CHIP I/O pin assignments.

  9. Figure 3.1 Digital logic technologies.

  10. Figure 3.2 Digital logic technology tradeoffs.

  11. Figure 3.3 Using a PLA to implement a Sum of Products equation.

  12. Figure 3.4 Examples of FPLDs and advanced high pin count package types.

  13. ALTERA MAX 7000 Architecture Figure 3.5 MAX 7000 macrocell.

  14. ALTERA MAX 7000 Architecture Figure 3.6 MAX 7000 CPLD architecture.

  15. Figure 3.7 FLEX 10K100 FPLD die photo, PIA interconnects are visible.

  16. Figure 3.8 FLEX 10K Logic Element (LE).

  17. Figure 3.9 Using a lookup table (LUT) to model a gate network.

  18. Figure 3.10 FLEX 10K Logic Array Block (LAB).

  19. Figure 3.11 FLEX 10K CPLD architecture.

  20. XILINX 4000 Architecture – A LU Table FPGA Figure 3.12 Silicon wafer containing XC4010E 10,000 gate FPGAs.

  21. XILINX 4000 Architecture – A LU Table FPGA Figure 3.13 Single XC4010E FPGA die showing 20 by 20 array of logic elements and interconnect.

  22. Figure 3.14 Xilinx 4000 Family Configurable Logic Block (CLB).

  23. Figure 3.15 CAD tool design flow for Field Programmable Logic Devices (FPLDs).

  24. Chapter 4: Tutorial II Figure 4.1 The tutor2.gdf schematic.

  25. Figure 4.2 8COUNT symbol online help file

  26. Figure 4.3 Internal VHDL code for dec-7seg function.

  27. Figure 4.4 Hierarchy display of the tutor2 design.

  28. . Figure 4.5 Enlarged view of tutor2 design showing bus connections.

  29. Figure 4.6 Timing analysis using Registered Performance option.

  30. Figure 4.7 Oscilloscope display of pushbutton switch contact bounce.

  31. Figure 4.8 Modified tutor2 design schematic.

More Related