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Combinational Logic: Other Gate Types. Gate classifications. Primitive gate - a gate that can be described using a single primitive operation type (AND or OR) plus an optional inversion(s). Complex gate - a gate that requires more than one primitive operation type for its description.
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Gate classifications • Primitive gate - a gate that can be described using a single primitive operation type (AND or OR) plus an optional inversion(s). • Complex gate - a gate that requires more than one primitive operation type for its description
primitive gates • NAND • NOR
NOR • NOT OR • Also common
NAND is Universal • Universal gate : Can express any Boolean Function using only this type of gate • Equivalents below
Sum of Products with NAND Easy to think of bubbles as canceling
NOR Also Universal • Dual of NAND
Buffer • No inversion • No change, except in power or voltage • Used to enable driving more inputs
Parity Function • How does parity work ? • Given 7- bit ASCII code for A (100 0001) • What is the ASCII code for A with even parity ? • Write truth table for two input even parity generator • What needs to be generated for parity bit? • What function of two inputs gives you this? • This is called: Exclusive OR function
Example Complex Digital Logic Gates: Exclusive OR/ Exclusive NOR Å = + X Y X Y X Y Å = + X Y X Y X Y • The Exclusive OR (XOR) function is defined as: • The eXclusive NOR (XNOR) function, otherwise known as equivalence is:
Symbols For XOR and XNOR • XOR symbol: • XNOR symbol: • Symbols exist only for two inputs
Truth Tables for XOR/XNOR Å Å X Y X Y X Y (X Y) º or X Y 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 • Operator Rules: XOR XNOR • The XOR function means: X OR Y, but NOT BOTH • Why is the XNOR function also known as the equivalence function, denoted by the operator ?
XOR Implementations Å = + X Y X Y X Y Y Y X X • The simple SOP implementation uses the following structure: • A NAND only implementation is: X Y X Y
XOR/XNOR (Continued) X Y Z X Y Z X Y Z X Y Z X Y Z Å X 0 X X 1 X Å = = Å X X 0 X X 1 Å = X Y Y X Å Å ) = = Å Å Å Å Å Å ( X Y Z X ( Y Z ) X Y Z • The XOR function can be extended to 3 or more variables. For more than 2 variables, it is called an odd function or modulo 2 sum (Mod 2 sum), not an XOR: • The complement of the odd function is the even function. • The XOR identities: Å Å = + + + = =
Question C 1 1 1 1 B 1 1 A 1 1 D • Draw the K-map of a 4 variable odd function
Example: Odd Function Implementation + + • Design a 3-input odd function F = X Y Zwith 2-input XOR gates
Example: Odd Function Implementation + + + + • Design a 3-input odd function F = X Y Zwith 2-input XOR gates • Factoring, F = (X Y) Z
Example: Odd Function Implementation X Y F Z + + + + • Design a 3-input odd function F = X Y Zwith 2-input XOR gates • Factoring, F = (X Y) Z • The circuit:
Example: Odd Function Implementation X Y F Z + + + + • Design a 3-input odd function F = X Y Zwith 2-input XOR gates • Factoring, F = (X Y) Z • The circuit: • Based on the above, given (X,Y,Z,F), then F would be the even parity bit for the three bits X,Y,Z. Hence, the circuit is an even parity generator.
Even Parity Generators and Checkers X Y P Z X Y E Z P • An even parity bit could be added to n-bit code to produce an n + 1 bit code: • Use an odd function to produce codes with even parity • Use odd function circuit to check code words with even parity • Example: n = 3. Generate even parity code words of length 4 withan odd function circuit (parity generator): • Check even parity code words of length 4 with odd function circuit • Operation: (X,Y,Z) = (0,0,1) gives(X,Y,Z,P) = (0,0,1,1) and E = 0.If Y changes from 0 to 1 betweengenerator and checker, then E = 1 indicates an error.
Odd Parity Generators and Checkers Similarly, an odd parity bit could be added to n-bit code to produce an n + 1 bit code • Use an even function to produce codes with odd parity • Use even function circuit to check code words with odd parity
Tri-State • Output w/ 3 states: H, L, and Hi-Z • High impedance • Behaves like no output connection if in Hi-Z (Hi Impedance) state • Allows connecting multiple outputs
Data Selector (2 to 1 Multiplexer) IN0 OL IN1 s Data Selection • If s = 0, OL = IN0, else OL = IN1
Data Selection Function Implementation with 3-State Logic IN0 OL EN0 S IN1 EN1 • Data Selection Function: If s = 0, OL = IN0, else OL = IN1 • Performing data selection with 3-state buffers: • Since EN0 = S and EN1 = S, one of the two buffer outputs is always Hi-Z plus the last row of the table never occurs.