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State Machine & Timing Design

State Machine & Timing Design. Finite State Machine(FSM) Mealy Machine Moore Machine FSM in VHDL More VHDL codes for FSMs Techniques for simple sequential logic design. 강의 내용. Finite State Machines (FSMs). Any circuit with memory is a finite state machine (FSM: 유한 상태 기계 )

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State Machine & Timing Design

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  1. State Machine & Timing Design

  2. Finite State Machine(FSM) Mealy Machine Moore Machine FSM in VHDL More VHDL codes for FSMs Techniques for simple sequential logic design 강의 내용 모바일컴퓨터특강

  3. Finite State Machines (FSMs) • Any circuit with memory is a finite state machine (FSM:유한 상태 기계) • Even computers can be viewed as huge FSMs • Design of FSMs involves • Defining states • Defining transitions between states • Optimization / minimization • Manual optimization/minimization is practical for small FSMs only 모바일컴퓨터특강

  4. Inputs Next State function Next State Present State Present Stateregister clock reset Output function Outputs Moore FSM • Output is a function of a present state only 모바일컴퓨터특강

  5. Moore Machine transition condition 1 state 2 / output 2 state 1 / output 1 transition condition 2 모바일컴퓨터특강

  6. Inputs Next State function Next State Present State Present Stateregister clock reset Output function Outputs Mealy FSM • Output is a function of a present state and inputs 모바일컴퓨터특강

  7. Mealy Machine transition condition 1 / output 1 state 2 state 1 transition condition 2 / output 2 모바일컴퓨터특강

  8. Moore vs. Mealy FSM (1) • Moore and Mealy FSMs can be functionally equivalent • Equivalent Mealy FSM can be derived from Moore FSM and vice versa • Mealy FSM has richer description and usually requires smaller number of states • Smaller circuit area 모바일컴퓨터특강

  9. Moore vs. Mealy FSM (2) • Mealy FSM computes outputs as soon as inputs change • Mealy FSM responds one clock cycle sooner than equivalent Moore FSM • Moore FSM has no combinational path between inputs and outputs • Moore FSM is more likely to have a shorter critical path 모바일컴퓨터특강

  10. 0 1 0 S0 / 0 1 S1 / 0 S2 / 1 reset 1 S0: No elements of the sequence observed S2: “10” observed S1: “1” observed Meaning of states: 0 Moore FSM - Example 1 • Moore FSM that recognizes sequence “10” 모바일컴퓨터특강

  11. 0 / 0 1 / 0 1 / 0 S0 S1 reset 0 / 1 S0: No elements of the sequence observed S1: “1” observed Meaning of states: Mealy FSM - Example 1 • Mealy FSM that recognizes sequence “10” 모바일컴퓨터특강

  12. clock 0 1 0 0 0 input S0 S1 S2 S0 S0 Moore S0 S1 S0 S0 S0 Mealy Moore & Mealy FSMs – Example 1 모바일컴퓨터특강

  13. FSMs in VHDL • Finite state machines can be easily described with processes • Synthesis tools understand FSM description if certain rules are followed • State transitions should be described in a process sensitive to clock and asynchronous reset signals only • Outputs described as concurrent statements outside the process 모바일컴퓨터특강

  14. Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs State Machine - Mealy Machine • Mealy Machine • 현재의 상태(Current State)와 현재의 입력(Inputs)에 의해 출력이 결정됨 모바일컴퓨터특강

  15. Reset 0/00 S0 1/10 0/01 S1 1/00 WindowAct / RiseShot, FallShot 입력 / 출력1, 출력2 Mealy FSM 의 해석– State diagram 해석 1. WindowAct신호가 0에서 1로 변하면 S1 state으로 전환, 이 때 output RiseShot을 1로, 2. WindowAct신호가 1에서 0으로 변하면 S0 state으로 전환,FallShot을 1로 만들어야 함. 3. State 전환이 없으면 output들은 모두 0 모바일컴퓨터특강

  16. Mealy Machine 구현 – Process 2개사용 Library ieee; Use ieee.std_logic_1164.all; ENTITY RiseFallShot IS PORT( clk : IN STD_LOGIC; reset : IN STD_LOGIC; WindowAct : IN STD_LOGIC; RiseShot, FallShot : OUT STD_LOGIC); END RiseFallShot; ARCHITECTURE a OF RiseFallShot IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk, reset) BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN s0 => IF WindowAct='1' THEN state <= s1; ELSE state <= s0; END IF; WHEN others => IF WindowAct='0' THEN state <= s0; ELSE state <= s1; END IF; END CASE; END IF; END PROCESS; 새로운 Data type “STATE_TYPE” 지정 같은 부분 Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs 모바일컴퓨터특강

  17. Mealy Machine 구현 – Process 2개 사용 PROCESS(state, WindowAct) BEGIN if( state= s0 and WindowAct='1') then RiseShot <='1'; else RiseShot <='0'; end if; if( state= s1 and WindowAct='0') then FallShot <='1'; else FallShot <='0'; end if; END PROCESS; END a; Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs 같은 부분 모바일컴퓨터특강

  18. Mealy Machine 구현 – Process 3개 사용 library ieee; Use ieee.std_logic_1164.all; ENTITY RiseFallShot_v2 IS PORT( clk : IN STD_LOGIC; reset : IN STD_LOGIC; WindowAct : IN STD_LOGIC; RiseShot, FallShot : OUT STD_LOGIC); END RiseFallShot_v2; ARCHITECTURE a OF RiseFallShot_v2 IS TYPE STATE_TYPE IS (s0, s1); SIGNAL State, NextState: STATE_TYPE; BEGIN PROCESS (State, WindowAct) BEGIN CASE State IS WHEN s0 => IF WindowAct='1' THEN NextState <= s1; ELSE NextState <= s0; END IF; WHEN others => IF WindowAct='0' THEN NextState <= s0; ELSE NextState <= s1; END IF; END CASE; END PROCESS; 같은 부분 Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs 모바일컴퓨터특강

  19. Mealy Machine 구현– Process 3개 사용 PROCESS(reset,clk) BEGIN IF reset = '0' THEN State <= s0; ELSIF clk'EVENT AND clk = '1' THEN State <= NextState; END IF; END PROCESS; process(State,WindowAct) begin if( State= s0 and WindowAct='1') then RiseShot <='1'; else RiseShot <='0'; end if; if( State= s1 and WindowAct='0') then FallShot <='1'; else FallShot <='0'; end if; end process; 같은 부분 Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs 같은 부분 모바일컴퓨터특강

  20. State Machine - Moore Machine • Moore Machine • 현재의 상태(Current State)만에 의해 출력(Outputs)이 결정됨 • “Moore is less” Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs 모바일컴퓨터특강

  21. 0 Reset S0 000 1 1 S1 010 0 1 S2 101 Moore Machine 해석– State diagram 상태 출력 입력 : WindowAct 출력 : y(2:0) 해석 1. WindowAct신호가 0일 때는 State의 변화가 없으며, 1일 때는 state의 변화가 S0->S1->S2->S0로 순환한다. 2. 출력신호 y(2:0)은 상태가 S0인 경우 “000”을 S1인 경우에는 “010”을 S2인 경우에는 “101”을 출력한다. 모바일컴퓨터특강

  22. Moore Machine 구현– Process 2개 사용 Library ieee; Use ieee.std_logic_1164.all; ENTITY MooreMachine IS PORT( clk, reset, WindowAct : IN STD_LOGIC; y : OUT STD_LOGIC_vector(2 downto 0)); END MooreMachine; ARCHITECTURE a OF MooreMachine IS TYPE STATE_TYPE IS (s0, s1,s2); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk, reset) BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN s0 => IF WindowAct='1' THEN state <= s1; ELSE state <= s0; END IF; WHEN s1 => IF WindowAct='1' THEN state <= s2; ELSE state <= s1; END IF; WHEN others => IF WindowAct='1' THEN state <= s0; ELSE state <= s2; END IF; END CASE; END IF; END PROCESS; 같은 부분 Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs 모바일컴퓨터특강

  23. Moore Machine 구현– Process 2개 사용 PROCESS(state) BEGIN CASE state IS WHEN s0 => y <= "000"; WHEN s1 => y <= "010"; WHEN others => y <= "101"; END CASE; END PROCESS; END a; Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs 같은 부분 모바일컴퓨터특강

  24. Moore Machine 구현– Process 3개 사용 Library ieee; Use ieee.std_logic_1164.all; ENTITY MooreMachine_v3 IS PORT( clk, reset, WindowAct : IN STD_LOGIC; y : OUT STD_LOGIC_vector(2 downto 0)); END MooreMachine_v3; ARCHITECTURE a OF MooreMachine_v3 IS TYPE STATE_TYPE IS (s0, s1,s2); SIGNAL state, NextState: STATE_TYPE; BEGIN PROCESS ( State, WindowAct) BEGIN CASE State IS WHEN s0 => IF WindowAct='1' THEN NextState <= s1; ELSE NextState <= s0; END IF; WHEN s1 => IF WindowAct='1' THEN NextState <= s2; ELSE NextState <= s1; END IF; WHEN others => IF WindowAct='1' THEN NextState <= s0; ELSE NextState <= s2; END IF; END CASE; END PROCESS; 같은 부분 Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs 모바일컴퓨터특강

  25. Moore Machine 구현– Process 3개 사용 같은 부분 PROCESS (clk, reset) BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN state <= NextState; END IF; END PROCESS; PROCESS(state) BEGIN CASE state IS WHEN s0 => y <= "000"; WHEN s1 => y <= "010"; WHEN others => y <= "101"; END CASE; END PROCESS; END a; Current State Combinational Logic F/F Next State Inputs Combinational Logic Outputs 같은 부분 모바일컴퓨터특강

  26. Moore FSM process(clock, reset) Inputs Next State function Next State Present StateRegister clock Present State reset concurrent statements Output function Outputs 모바일컴퓨터특강

  27. Mealy FSM process(clock, reset) Inputs Next State function Next State Present State Present StateRegister clock reset Output function Outputs concurrent statements 모바일컴퓨터특강

  28. 0 1 0 S0 / 0 1 S1 / 0 S2 / 1 1 reset 0 Moore FSM - Example 1 • Moore FSM that Recognizes Sequence “10” 모바일컴퓨터특강

  29. Moore FSM in VHDL (1) TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state; U_Moore: PROCESS (clock, reset) BEGIN IF(reset = ‘1’) THEN Moore_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF; 모바일컴퓨터특강

  30. Moore FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’; 모바일컴퓨터특강

  31. 0 / 0 1 / 0 1 / 0 S0 S1 reset 0 / 1 Mealy FSM - Example 1 • Mealy FSM that Recognizes Sequence “10” 모바일컴퓨터특강

  32. Mealy FSM in VHDL (1) • TYPE state IS (S0, S1); • SIGNAL Mealy_state: state; • U_Mealy: PROCESS(clock, reset) • BEGIN • IF(reset = ‘1’) THEN • Mealy_state <= S0; • ELSIF (clock = ‘1’ AND clock’event) THEN • CASE Mealy_state IS • WHEN S0 => • IF input = ‘1’ THEN • Mealy_state <= S1; • ELSE • Mealy_state <= S0; • END IF; 모바일컴퓨터특강

  33. Mealy FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Mealy_state <= S0; ELSE Mealy_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’; 모바일컴퓨터특강

  34. resetn w = 1 ¤ ¤ A z = 0 B z = 0 w = 0 w = 0 w = 1 w = 0 ¤ C z = 1 w = 1 Moore FSM – Example 2: State diagram 모바일컴퓨터특강

  35. Next state Present Output z state w = 0 w = 1 A A B 0 B A C 0 C A C 1 Moore FSM – Example 2: State table 모바일컴퓨터특강

  36. Moore FSM with 2’s Processes process(clock, reset) Input: w Next State function Next State Present StateRegister Present State: y clock resetn Output: z concurrent statements Output function 모바일컴퓨터특강

  37. Moore FSM – Example 2: VHDL code (1) USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN 모바일컴퓨터특강

  38. Moore FSM – Example 2: VHDL code (2) CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; 모바일컴퓨터특강

  39. Moore FSM – Example 2: VHDL code (3) END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ; 모바일컴퓨터특강

  40. Moore FSM with 3’s Processes process (w, y_present) Input: w Next State function Next State: y_next process (clock, resetn) Present StateRegister Present State: y_present clock resetn Output: z concurrent statements Output function 모바일컴퓨터특강

  41. Alternative VHDL code (1) ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; 모바일컴퓨터특강

  42. Alternative VHDL code (2) WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (clock, resetn) BEGIN IF resetn = '0' THEN y_present <= A ; ELSIF (clock'EVENT AND clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ; 모바일컴퓨터특강

  43. resetn / w = 1 z = 0 / / w = 0 z = 0 w = 1 z = 1 A B / w = 0 z = 0 Mealy FSM – Example 2: State diagram 모바일컴퓨터특강

  44. z Next state Output Present state w = 0 w = 1 w = 0 w = 1 A A B 0 0 B A B 0 1 Mealy FSM – Example 2: State table 모바일컴퓨터특강

  45. Mealy FSM with 2’s Processes process(clock, reset) Input: w Next State function Next State Present State: y Present StateRegister clock resetn Output: z Output function concurrent statements 모바일컴퓨터특강

  46. Mealy FSM – Example 2: VHDL code (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Mealy IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END Mealy ; ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN 모바일컴퓨터특강

  47. Mealy FSM – Example 2: VHDL code (2) CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; 모바일컴퓨터특강

  48. Mealy FSM – Example 2: VHDL code (3) END IF ; END PROCESS ; WITH y SELECT z <= w WHEN B, z <= ‘0’ WHEN others; END Behavior ; 모바일컴퓨터특강

  49. Timing Design - 강의순서 • State Machine 응용 • Shift Register 응용 • Counter 응용 주어진 타이밍도로부터 회로를 설계하는 방법을 다양한 형태의 접근 방법을 통해 습득한다. 각종 디바이스의 데이터 북상에 나타나는 타이밍 도의 이해를 위한 더욱 심화된 지식을 배양한다. 모바일컴퓨터특강

  50. Timing Design –State Machine Application (1) 1. 아래와 같은 Timing 입출력 파형을 갖는 회로를 설계해보자 • 해석 : WindowAct신호가 0에서 1로 변하는 순간부터 다음 clock의 rising edge 까지 RiseShot을 1로 만들고 • WindowAct신호가 1에서 0으로 변하는 순간부터 다음 clock의 rising edge 까지 FallShot을 1로 만들어야 함. 모바일컴퓨터특강

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