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News from CERN Underground

News from CERN Underground. DMB firmware upgrade: L1A fine latency setting implemented (1bx granularity) ALCT firmware fixed: ME+1/3 chambers have correct DAQ format TMB “clct_stagger” bit corrected in xml file Golden run #39924 taken with most station +1, +2, and +3 chambers (201 CSCs)

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News from CERN Underground

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  1. News from CERN Underground • DMB firmware upgrade: • L1A fine latency setting implemented (1bx granularity) • ALCT firmware fixed: • ME+1/3 chambers have correct DAQ format • TMB “clct_stagger” bit corrected in xml file • Golden run #39924 taken with most station +1, +2, and +3 chambers (201 CSCs) • See: https://twiki.cern.ch/twiki/bin/view/CMS/CSCGoldenRunList • Focus underground currently on: • Fixing “problem” CSCs • Alignment of CSC triggers at Track Finder • Making configuration more robust, including Track Finder… • Runs beginning to be taken including all CSCs G. Rakness (UCLA)

  2. Coming Up Underground… • Cosmic Run at 0 Tesla (CR0T) • April 21 (09h00) – 28 (08h00) (I’m away) • May 5 (09h00) – 12 (08h00) • Have heard rumors that 1st week may be cancelled… • Physical location of CSCs during CR0T not yet specified: likely to be meters from barrel • Overlap with Drift Tubes will be minimal and hard to interpret • Thursday Dan and I will set local CSC trigger latency to be = Global latency from Middle of March • Tools exist to monitor L1A latency online • Will add tool to accommodate L1A latency change in xml file, if it changes… • YE+1 will remain off ~all week • Closure tests against barrel G. Rakness (UCLA)

  3. TMB Firmware Loading • Valeri Sytnik going to work on button to selectively power off CCB • Should allow for remote recovery of TMBs whose firmware has been malformed • I have found that TMB boot register bit 14 correctly reflects TMB FPGA state. Mike Matveev has found that it does not… • Differences include: • Mike loads through front panel JTAG cable, unplugs cable, power cycles, looks at bit 14 (N.B. He has the shunt set so that the FPGA does not control the VME bus…) • I load via VME, kill the process, hard reset, look at bit 14 • ? • To be done: ALCT fast and slow control downloading… G. Rakness (UCLA)

  4. Other Stuff… • Discussed with peripheral crate, FED, run control folks how to configure the CSCs… • Note: did not include the Track Finder… • Essential features include… • Configuration by hard reset • Explicit configuration checks • L1 Data Quality Monitoring workshop today • http://indico.cern.ch/conferenceDisplay.py?confId=31662 • It was thought that CSC Trigger Primitives, in the context of the L1 trigger, should have their data quality monitored as the input to the Track Finder… • Hence, CSC TPG DQM for L1 trigger falls under the aegis of the CSC TF group…. • Under discussion… G. Rakness (UCLA)

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