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PART –B UNIT 5

PART –B UNIT 5. MEMORY SYSTEM. MEMORY SYSTEM. Memory Types. Primary Memory Read/Write Memory (RAM) 1) SRAM (Static RAM) 2) DRAM(Dynamic RAM) Read Only Memory (ROM) 1 ) PROM (Programmable ROM) 2)EPROM (Erasable PROM) 3) EEROM(Electrically EPROM)

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PART –B UNIT 5

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  1. PART –BUNIT 5 MEMORY SYSTEM

  2. MEMORY SYSTEM

  3. Memory Types • Primary Memory • Read/Write Memory (RAM) 1) SRAM (Static RAM) 2) DRAM(Dynamic RAM) • Read Only Memory (ROM) 1) PROM (Programmable ROM) 2)EPROM (Erasable PROM) 3) EEROM(Electrically EPROM) 4) Flash Memory • Secondary Memory • Magnetic Storage ex: disks or tape drive • Optical storage ex: CD, DVD

  4. RAM • Static RAM • Storage cells are made up of FLIP FLOPs • Each bit storage requires 6 Transistors • Capacity is less ie in KB • Faster • Dynamic RAM • Information is stored as charge on G-S capacitance of Transistor • Each bit storage requires 1 Transistor • Higher capacity than SRAM ie MB • Refreshing ckt is required Both SRAM & DRAM are Volatile Memory

  5. ROM • Read-O nly-Memory ( R O M ) : The information is stored permanently during manufacture. For example, the "BOOTSTRAP loader" in the computer is stored in a ROM. • PROMs - Programmable ROMs, where the user can modify the content once. • EPROMs-Erasable PROMs, where the contents can be erased using UV rays • EEPROMs- Electrically Erasable PROMs, wherein the contents can be erased without the need of removing the chip from the board. All the above memory system are nonvollatile, that is, they retain the information even when supply is off

  6. BASIC CONCEPTS OF PRIMARY MEMORY • Maximum size of the memory in a computer system is determined by the number of address lines of the processor. For example:16 address lines is capable of addressing up to 2^16 = 64K memory location In general, for k-bit address, the memory capacity is 2^k locations. Generally, the memory is byteaddressable.

  7. Main Memory Organization in 32 bit Computer

  8. Connection of the main memory to the processor • The number of bits stored or retrieved in one memory access is called the word length of the computer. • Data transfers between memory and the processor take place through the use of two registers MAR and MDR • If MAR is k-bit long, the memory unit can contain up to 2^k addressable locations. • If MDR is n bits long, n bits of data can be transferred between memory and processor at a time. • The external bus also includes the control lines Read/Write (R/W) and Memory Function completed (MFC) for co-coordinating the data transfer. For data transfer, the address of the memory location in MAR is sent out on the address lines. R/W is asserted low for store (write) operation and high for load (read) operation.

  9. Connection of the main memory to the processor

  10. Some of the terminologies used are: • Speed of Memory Memory access time • Time that elapses between the initiation of a memory operation and the completion of that operation • e.g. the time between READ and MFC signals Memory cycle time • The minimum time delay required between the initiation of two successive memory operations • e.g. the time between two successive Read operations Random Access Memory (RAM): Any location can be accessed (randomly) in a fixed amount of time irrespective of location.

  11. Cache memory Small, fast memory used to reduce memory access time. It holds the currently active segments of a program and its data. • Virtual Memory: A concept used to increase the apparent size of the physical memory when large program segment is to be executed. • Static Memory Versus Dynamic Memory

  12. Semiconductor RAM Memories • Available in a wide range of speeds • Memory cells are usually organized in the form of an array with each cell capable of storing one bit of information. • each row of cells constitute a memory word and all cells of a row are connected to a common‘ line referred to as word line, • The address decoder selects only one of the word lines at a time and all cells in that row will be enabled. • The cells in each column are connected to Sense/write circuit by two bit lines. • The Sense/write circuits are connected to the data input/output lines of the chip. • During a Read operation, these circuits sense or read the information stored in the cells selected by a word line and transmit this information to the output data lines. • During a write operation, the input information is stored in the cells of the selected word

  13. Organization of bit cells in a memory chip

  14. The above memory chip consists of 16 words of 8 bits each • Thus storing 128 bits. This is referred to as 16 x 8 organization. • The data input and data output of each Sense/Write circuit are connected to a single bidirectional data line to reduce the number of pins required. • These data lines are connected the data bus of the processor. • Two control lines R/W and CS are provided. , • R/W specifies Read or write operation and chip select (CS) line is used to enable particular memory chip in a multichip memory system • This memory chip requires 14 external connections (4 address lines, 8 data lines, R/w and cs lines) apart from supply connections. • For example, lK memory chip, which is organ ized as .128 x 8 memory. we see that it requires 19 external connections (7 address lines, 8 data lines, 2 control lines, one ground pin and one supply pin). So, this kind of arrangement results in large physical size when memory size is increased.

  15. 5-bit row address W o W 1 32 x 32 : 5-bit memory cell : decoder array : W 31 Sense/ Write Circuitry . . . . 10-bit address multiplexers 32-to-1 R/ W demultiplexers 1-to-32 CS (1 input and 1 output) 5-bit column address Data Data input output Organization of 1K x 1 memory chip

  16. An alternative arrangement which can be used to red.uce the pin count and increase the memory size is as shown in previous slide • Here, the lK (1,024) cells are arranged as 1K x 1 format • which requires 15 connections (10 address lines, 1 data line, 2 control lines and 2 supply tines). • The 10-bit address line is divided into groups of 5 bits each to form the row and column addresses for the cell array. • A row address selects a row of 32 cells , all are accessed in parallel. But according to the column address only one of these cells is connected to the external data line

  17. Static RAM cell ( SRAM ) Two invertors connected back to back to form a latch. After latching the latch holds the data even without ‘b’ and T1 & T2 can be disabled (logic 0). Static: capable of retaining the state as long as the power is applied. How to Read & Write bit cell ?

  18. A CMOS memory cell T3 & T5 pair & T4 & T6 pair form the inverters How to Read & Write ?

  19. Dynamic RAM cell ( DRAM) • SRAMs are fast but costly ( several transistors) • Less expensive RAMs with simper cell are available • But don’t retain their state indefinitely ( dynamic ! ) • Information is stored in the form of charge on a capacitor. • The charge can be can be maintained for only tens of milliseconds ! • So contents must be periodically refreshed by restoring the capacitor charge to its full value.

  20. Dynamic RAM cell. . . So simple Only one T & one C Less Space, High density But refreshing !!! Bit Line Word Line T C During read operation the capacitor discharges ! During idle condition also the capacitor discharges !

  21. 1M1-bit Dynamic Memory Chip 1M1-bit Row/Column address are controlled by RAS and CAS Row/Column address multiplexed RAS: Row Address Strobe CAS: Column Address Strobe

  22. A 2 M x 8 dynamic memory chip

  23. The organization of a 16 Megabit DRAM structured as 2M x 8 memory The cells are organized as 4K x 4K array. The 4K (4096) cells in each row are divided into 512 groups of 8-bits each, i.e., the row can store 512 bytes of data‘ Thus, 12 address bits are required to select a row. Another 9 bits are needed to specify a group of 8 bits in the selected row. Thus, a 21'-bit address is needed to access a byte. The high-order 12 bits and the low-order 9 bits of the address constitute the row and column address of a byte. During a Read or Write operation, the row address is loaded into the row address latch in response to a signal on Row Address Strobe (RAS) input of the chip. Then, a read operation is initiated, in which all cells on the selected row are read and refreshed.

  24. Now, the column address is applied to the address pins and loaded into column address latch using Column Address Strobe (CAS) signal. The information in this latch is decoded and the appropriate group of 8 Sense/Write circuits are selected. If the R/W signal indicates a Read operation, the output of the selected circuit is transferred to the data lines D7-Do. For a Write operation, the information on the D7-Do lines is transferred to the selected circuits. This information will overwrite the contents of the selected cells in the corresponding 8 columns.

  25. Row and Column addresses are multiplexed ! • First row then column address ! • Refresh circuit is built in the DRAM chip • Size may range from 1 M to 256 Mbits or greater. • Say a 64 Mbit chip may be organized as 16M x 4, 8M x 8, or 4M x 16.

  26. Refreshing: Applying a Row address causes the cells on the corresponding row to be read and refreshed during both READ/ Write operation To maintain the contents of DRAM Each row of cells must be accessed periodically (every 1 ms) Refresh ckt perform this operation Automatically Asynchronous DRAM: Timing Of the memory device is controlled using a special memory control signals RAS and CAS

  27. Fast Page Mode of DRAM • In a selected row a byte is accessed by column address. • A simple modification can make it possible to access the other bytes in the same row without having to reselect the row. • A latch can be added at the output of the sense amplifier in each column. • It is only necessary to apply different column addresses to place different bytes on that row • Block transfer of data are referred as Fast Page mode.of operation

  28. Synchronous DRAMs • Operation is directly synchronized with the clock signal – Synchronous DRAM, (SDRAM). • Mode register is to select various operating modes like burst transfer/fast page mode, word by word transfer. Control information The operating modes of SDRAM (like burst mode or step by step mode) can Be selected by writing control information into a mode register. The burst operations use block transfer capability as the fast page mode feature. It is not necessary to provide external pulses on the CAS line to select successive columns. The control signals are provided internally using a column counter and the clock signal. New data can be placed on the data lines in each clock cycle. All operations are Synchronized with rising edge of the clock.

  29. SDRAM Refersh Counter Cell Array Row Address Latch Row Decoder Row/Column Address Read/Write Circuits & Latches Column Address Latch Column Decoder Clock RAS CAS R/W CS Mode Register And Timing Control Data Input Register Data output Register Data

  30. The timing diagram for a burst read cycle of length 4 is shown in previous slide The row address is latched under the control of RAS signal. The memory activates the selected row after 2 or 3 clock cycles. Then, the column address is latched using CAS signal. After one cycle delay, the first set of data bits is placed on the data lines. The SDRAM automatically increments the column address to access the next three sets of bits in the selected row. These are put on the data lines during next three clock cycles.

  31. Memory Latency, Bandwidth • Latency • The amount of time it takes to transfer a word of data to or from the memory. • Measured easily in case of single word access. • Bandwidth • A performance measure in terms of the number of bits/bytes that can be transferred in one second. • Depends on the block size, also the data bus width & speed of the bus.

  32. DDR SDRAMs • Double Data Rate – faster version of SDRAM • Transfers the data on both edges of the clock. • Latency is same as SDRAM, but transfers with double data rate

  33. Structure of Larger Memories Static Memory System Dynamic Memory System

  34. Structure of Larger Memories Memory expansion: How several memory chips can be connected to form a Larger memory required in a system. This is known as memory expansion. It can be done in two ways: 1) size (capacity) expansion 2) word length expansion. In some cases, both may be required. We have used active-low chip select signals. Read/Write signals are not shown, but are applied depending on the type of operation.

  35. Logic diagram for expanding the size of the memorykeeping the word length same.

  36. Logic diagram for expanding the word length of the memorykeeping the size constant

  37. Expansion of Memory size as well as Word length 64K8-bit Using 16 K x 1 8-bit I/O

  38. Implementation of 2 M x 32 module using 512 K x 8 static chips 2M x 32 requires total 21 address lines Each row contains 32 bit information (data) The total number of rows = 2M The total number of columns = 32 In order to implement this 2M x 32 module using 512K x 8 static chip, we need the following requirements Number of address lines required is 19 (for 512k) and 2 address lines are used to select the particular memory chip (out of 4). So total 21 address lines are required. In order to get 2M rows we need to connect Four rows 512K x 8 memory chips In order to get 32 columns (32 bit word) , we need to connect Four 512K x 8 in each row. Therefore total 16 512K x 8 Memory chips are required to, obtain 2M x 32 memory module

  39. Each chip has one control input called Chip select. When Chip select set to 1 indicates that, the chip to accept data from or place data on its data lines. The data outputs have tri-state buffers. Only the selected chip places the data on the data output line, while all other outputs remain in high impedance state.

  40. Implementation of 2 M x 32 module using 512 K x 8 static chips

  41. Dynamic Memory System The organization of large dynamic memory system is same as that of static system. Implementation is done using Memory Modules Systems have a main memory of at least 128 MB Larger memory leads to better performance. If larger memory is built by by placing DRAM chips directly on the system motherboard, it will occupy large physical space, and also free space is to be allocated for future expansion. This constraints led to the development of memory units known as SIMMS(Single In line Memory Module) and DIMMS( double in line memory module) These modules are collection of several memory chips on a separate small board that plugs vertically into a single socket on the motherboard For example: 4M x 32, 16M x 32, 32M x 32bit DIMMS all use the same 100 pin socket. All these modules occupy min. space on a motherboard and also they allow easy expansion by replacement.

  42. Memory System Considerations • Type of memory used - Application Dependent • Cost, Speed, Power dissipation, Size of the chip • Static RAMs are used only when very fast operation is the primary requirement • Their cost & size adversely affected by the complexity of the circuit that realizes the cell • Used in cache memories

  43. Dynamic RAMs are predominant choice for implementing computer main memories. • The high densities achievable in theses chips make large memories economically feasible.

  44. Memory controller Row/Column Address Memory Processor Address Memory controller RAS R/W CAS R/W Request CS Clock Clock

  45. Processor issues all bits of an address at the same time. Multiplexing is performed by the Memory controller circuit, placed between Processor & DRAM. Processor sends the address & R/W signal and then issues a request signal to the controller to indicate that memory access is needed. Controller then forwards the row and column portions of the address to the memory and generates RAS and CAS signals. It also sends R/w and active low chip select CS signals to the memory. If memory is SDRAM then clock signals are needed. Data lines are directly connected between Processor and memory If DRAM chips do not contain any refreshing ckts, then controller will provide this information. Controller contains a refresh counter that provides successive row addresses to refresh all rows within a specified time.

  46. Refresh Overhead • Dynamic memories requires frequent refreshing • The frequency may be 16ms to 64 ms • Consider SRAM with 8K (8192) rows • Say takes four clock cycles to access a row • So, 8192 x 4 = 32,768 cycles to refresh all rows • At f = 133 MHz the time needed to refresh all rows is 32,768/133M = 246 μs. • So refreshing takes 0.246 ms in each 64ms time interval. • So refresh overhead is 0.246/64 = 0.0038 • So 0.4 percent of the total time available for accessing the memory is used for refreshing. 64ms 100 % 0.246ms ?

  47. RAMBUS Memory Performance depends on latency, bandwidth and speed. Performance can be improved by increasing the width of the bus. But this requires additional space on the motherboard.(to widen the data bus) and also expensive Alternative method is to implement a narrow bus which is faster. This type of bus was designed by Rambus Inc. This design is called RAMBUS. Key feature of this technique is differential signaling, That is instead of using signals with 0 or 1 (Vcc) volts, the signals consist of smaller voltage swings around a reference voltage Vref. The ref. Voltage is 2V and the two logic values are represented by 0.3V swings below and above Vref.This type of signaling is generally referred as Diff signaling. Small voltage swings takes less transition time which allows high speed transmission.

  48. Read-Only Memories (ROM) • There are many applications that need memory devices which retain the stored information even if power is turned off. • The boot program is such an example. • Extensively used in embedded systems. • Different types of nonvolatile memory have been developed. • The contents of such memory can be read as if they were SRAM or DRAM. • But, a special writing process is needed to place the information into this memory. • Normal operation of these memory is only reading data.

  49. ROM (Read Only Memory) cell Bit Line “The bit line is connected through a resister to the power supply “ To read the cell the word line is to be made ‘1’ & the transistor closes if P is closed ! So the bit line will be ‘0’ Else transistor will be off ( open) so the bit line will be ‘1’ Word Line T Connected to store a 0 Not connected to store a 1 P “P can be fused only once during fabrication”

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