DKT 122/3 DIGITAL SYSTEM 1

1. DKT 122/3DIGITAL SYSTEM 1 WEEK #12 LATCHES & FLIP-FLOPS

2. Topic Outlines • Latches & Flip-Flops • Differences between Latches and Flip-Flops • Types of Latches and Flip-Flops • Edge-Triggered Flip-Flops • Flip-Flop Operating Characteristics

3. Introduction • Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops.

4. Latches & Flip-Flops Differences between Latches and Flip-Flops • Latches • The output of a latch depends on its current inputs and on its previous output and its change of statecan happen at any timewhen its inputs change. • Flip-Flops • The output of a flip-flop also depends on current inputs and its previous output but the change ofstateoccurs at specific timesdetermined by a clock input.

5. Latches & Flip-Flops Types of Latches and Flip-Flops • Latches • S-R (SET-RESET) Latch • Gated S-R Latch • Gated D-Latch • Flip-Flops • Edge-Triggered S-R Flip-Flop • Edge-Triggered D Flip-Flop • Edge-Triggered J-K Flip-Flop

6. Latches • Type of temporary storage device that has 2 stable (bi-stable) states • Similar to flip-flop – the outputs are connected back to opposite inputs • Main difference from flip-flop is the method used for changing their state • Types: S-R latch, Gated/Enabled S-R latch and Gated D latch

7. Latches S-R (SET-RESET) Latch Active-HIGH input S-R Latch Active-LOW input S-R Latch

8. Latches S-R Latch Logic symbols

9. Latches S-R Latch Negative-OR equivalent of the NAND gate S-R latch

10. Latches S-R Latch Truth table for an active-LOW input S-R latch Question: What is the truth table for an active-HIGH input S-R latch?

11. S-R Latch • The three modes of basic latch operation • SET • RESET • no-change & • the invalid • condition

12. Latches Waveforms S-R Latch Assume that Q is initially LOW

13. Latches Gated S-R Latch • A gate input is added to the S-R latch to make the latch synchronous. • In order for the set and reset inputs to change the latch, the gate input must be active(HIGH/Enable). • When the gate input is low, the latch remains in the hold condition.

14. Latches Gated S-R Latch

15. S R G Q Q’ Comment 0 0 0 Q Q’ Hold 1 0 0 Q Q’ Hold 0 1 0 Q Q’ Hold 1 1 0 Q Q’ Hold 0 0 1 Q Q’ Hold 1 0 1 1 0 Set 0 1 1 0 1 Reset 1 1 1 0 0 Not allowed Latches Truth-table Gated S-R Latch

16. Latches Waveform Gated S-R Latch 2 3 1 4 5

17. Latches Waveform Gated S-R Latch 2 3 1 4 5 reset set set reset set

18. S-R latch is used to eliminate switch contact bounce Latches Application Gated S-R Latch

19. Latches (74LS75) Gated D Latch • The D (data) latch has a single input that is used to set and to reset the flip-flop. • When the gate is high, the Q output will follow the D input. • When the gate is low, the Q output will hold.

20. Latches (74LS75) Gated D Latch

21. Latches (74LS75) Waveform Gated D Latch The output follows the input when the gate is high but is in a hold when the gate is low.

22. Flip-Flops • Flip-flops are synchronous devices • Synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK) • An edge-triggered flip-flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) • Three types of edge-triggered flip-flops: • S-R Flip-Flops • D Flip-Flops • J-K Flip-Flops

23. Flip-Flops Edge-triggered flip-flop logic Positive edge-triggered Negative edge-triggered (bubble at C input)

24. 1 Clock signal 0 Clock Cycle Time Falling edges of the clock (Negative-edge triggered) Rising edges of the clock (Positive-edge triggered) Flip-Flops Clock signals and synchronous sequential circuits A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

25. Flip-Flops Edge-triggered S-R Flip-Flop The basic of S-R flip-flop consist of 2 NOR gates with the outputs cross-coupled to the inputs Cross-NOR S-R Flip-Flop

26. Flip-Flops Edge-triggered S-R Flip-Flop Note: Flip-flop cannot change state except on the triggering edge of a clock pulse. When S=R=1, invalid condition exists

27. Flip-Flops Edge-triggered S-R Flip-Flop (+ve edge) • = clock transition LOW to HIGH X = irrelevant (“don’t care”) Q0 = output level prior to clock transition -ve edge?

28. Flip-Flops Edge-triggered D Flip-Flop • Addition of an inverter to an S-R flip-flop creates a basic D flip-flop QUESTION: What is the condition of this S-R flip-flop? A positive-edge triggered D flip-flop

29. Flip-Flops Edge-triggered D Flip-Flop (Function of +ve e-t) SET • If there is a HIGH on the D input when a clock pulse is applied, the flip-flop will SET and the HIGH on the D input is stored by the flip-flop on the positive-going edge of the clock pulse (In the SET state, flip-flop is storing 1) RESET • If there is a LOW on the D input when a clock pulse is applied, the flip-flop will RESET and the LOW on the D input is stored by the flip-flop on the positive-going edge of the clock pulse (In the RESET state, flip-flop is storing 0)

30. Flip-Flops Edge-triggered D Flip-Flop (+ve e-t) Truth Table  = clock transition LOW to HIGH

31. Flip-Flops Edge-triggered J-K Flip-Flop • Function of J-K Flip Flop is identical to that of the S-R flip flop in the SET, RESET and no-change conditions of operation • The difference is that the J-K flip-flophas no invalid states as does the S-R flip-flop • On each successive clock spike, the flip-flop changes to the opposite state. This mode is called toggle operation

32. Flip-Flops Edge-triggered J-K Flip-Flop Simplified logic diagram for a positive edge-triggered J-K flip flop

33. Flip-Flops Edge-triggered J-K Flip-Flop Truth Table for positive edge-triggered J-K flip-flop  = clock transition LOW to HIGH Q0 = output level prior to clock transition

34. Flip-Flops Operating Characteristics Propagation delay time • Define as the interval of time required after an input signal has been applied for the resulting output change to occur tPLH Propagation delay tPLH as measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output

35. Flip-Flops Operating Characteristics Propagation delay time tPHL Propagation delay tPHL as measured from the triggering edge of the clock pulse to the HIGH-to-LOW transition of the output

36. Flip-Flops Operating Characteristics Set-up time (ts) • Define as the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop

37. Flip-Flops Operating Characteristics Hold time (th) • Define as the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop

38. Flip-Flops Operating Characteristics Maximum Clock Frequency (fmax) • The highest rate at which a flip-flop can be reliably triggered. • At clock frequencies above the maximum, the flip-flop would be unable to respond quickly enough, and its operation would be impaired Power dissipation • P = Vcc x Icc END