The Belle SVD Trigger

1. The Belle SVD Trigger Tom Ziegler on behalf of the Belle SVD group  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 • The SVD 2.0 Update • The Front-End Readout Electronics • Level 0 & 1 Trigger • Level 1.5 Trigger • Summary The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 1

2. SVD 2.0 SVD 1.4 The Belle detector The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 2

3. Update SVD 1.4 => SVD 2.0 • Increase radiation hardness of the front-end readout chip:0.8m => 0.35m CMOS process • Stable > 10 MRad! • Better polar angle coverage:23°-139° => 17°-150° • Closer to beam pipe (3->2.1cm) • increasing peak luminosity:8.256  1033 cm-2 s-1 (28-oct-2002) • Include trigger capability in front-end chip The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 3

4. The Readout Electronics • 4 layers (6, 12, 18, 18) • 54 ladders, • 108 halfladders DSSD Hybrid, VA1TA PCI and DAQ Repeater System Trigger L0&L1 FADC Trigger L1.5 (108*512)*2 = 110.592 channels The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 4

5. slow Shaper S/H fast Shaper Discr. PA Multiplexer 128x 128x 1x ! Hold Analog out Threshold Trigger out Front-end Electronics FE readout chips: VA1TA, IDE AS Each chip reads out 128 DSSD channels. Trigger capability is included in the ASIC. The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 5

6. The Readout Electronics • 4 layers (6, 12, 18, 18) • 54 ladders, • 108 half ladders DSSD Hybrid, VA1TA PCI and DAQ Repeater System TA signal, granularity of 128 strips Trigger L0&L1 FADC Trigger L1.5 (108*512)*2 = 110.592 channels The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 6

7. Level 0 and Level 1 Trigger We take advantage of the trigger capabilities of the front-end readout electronics (VA1TA). Resolution not very good, but very fast decision possible ( <600ns for L0 / <2.5s for L1). ToF trigger Global L0 CDC trigger SVD TA SVD-CDCmatching Global L1 CDC Other SubS. The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 7

8. The Readout Electronics • 4 layers (6, 12, 18, 18) • 54 ladders, • 108 half ladders DSSD Hybrid, VA1TA PCI and DAQ Repeater System VA analog signals, full granularity Trigger L0&L1 FADC Trigger L1.5 (108*512)*2 = 110.592 channels The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 8

9. IP 3.2cm wedge The Level 1.5 r-z-Trigger After 25 s all information are available from the FADC- system and can be used for a trigger 1.5 decision with a very good tracking resolution! Mainly reject beam gasevents that do not comefrom the primary vertex. Generate MC eventsand record ‘trigger terms’for each of 18 wedges. The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 9

10. The Trigger Logic Resolution which probably will be used: Layer 1/4: merge 32 strips to 16 segments on each wafer Layer 2/3: merge 16 strips to 32 segments on each wafer  We see all the gapsbetween wafers. Single track efficiency < 80%! => 4/4 too simplistic Goal: at least 90% The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 10

11. Improve efficiency Consider 3/4 terms (one layer missing)  => 98% efficient, but not very goodrejection of background events!  Try 3/4 terms and demand 1. layer => Overall efficiency 95% in good region (but more than 20,000 trigger terms). The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 11

12. Some statistical tricks Some of the logic terms are contained in others, e.g.: 20 22 20 2020 21 20 20 20 22 19 2020 22 20 18 Reduce number of terms by 25%. Number of hits in each trigger term in simulation, e.g.: 15 17 15 15 1634x15 16 15 15 1034x 15 17 14 15 341x15 17 15 13 11x Skip all trigger terms with few hits!=> skip terms without losing much efficiency The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 12

13. Implementation of Trigger Logic 4/4 terms 79.8% 21449 terms 3/4 terms 98.0% 23867 terms 3/4 terms (with inner layer) 95.3% 23867 termsstrip terms contained in others 95.3% 13474 termsstrip terms with #hits <50 95.3% 10105 termsstrip terms with #hits <100 95.1% 8272 termsstrip terms with #hits <500 93.1% 5452 terms strip terms with #hits <750 90.5% 2497 terms single track efficiency Implementation of trigger logicin Xilinx FPGAs on a 9U VME board. number of trigger terms The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 13

14. FADC DOCK T1.5 FEC CDC ToF TDM GDL SEQ TTM Further improvement Introduce Trigger 1.5 Buffer Board Merging of SVDwith CDC and ToFinformation! monitoring Level 1.5 trigger decision Up to 128 bits T1.5BB 1 bit for each of the 18 sectors Up to 64 bits Start of data transfer monitoring data data data The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 14

15. The Trigger System The different trigger levels will be: L0 0.6 s SVD, ToF, CDC < 10kHz L1 2.5 s SVD, CDC, ECL < 1kHz L1.5 25 s SVD, (ToF, CDC) DAQ read-out The SVD will play a central role in the Belle trigger system! The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 15

16. Summary Upgrade to SVD 2.0 allows substantial improvements in the trigger capabilities for the Belle detector! The implementation of the system with Xilinx FPGAs and overall setup is very flexibleand there is still room for improvement to deal with the increasing luminosities of the KEKB accelerator. The system will be tested the next months in an overall system integration test with the rest of the SVD readout system and is ready for installation in the next shutdown. The Belle SVD Trigger  Tom Ziegler  Vertex 2002  Kailua-Kona, Hawaii, 4-8th nov 2002 16