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Centro de Informática – UFPE Pernambuco, Brazil

Heracles Project. Centro de Informática – UFPE Pernambuco, Brazil. Medical Analysis Defects in the retina , EEG, ECG, EMG, EOG, ... Digital processing of signals Astronomy Vibration Analysis of musical instruments Geology Measure and analyze seismic waves. Motivation. The Problem.

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Centro de Informática – UFPE Pernambuco, Brazil

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  1. Heracles Project Centro de Informática – UFPE Pernambuco, Brazil

  2. Medical Analysis Defects in the retina, EEG, ECG, EMG, EOG, ... Digital processing of signals Astronomy Vibration Analysis of musical instruments Geology Measure and analyze seismic waves Motivation

  3. The Problem • Signal and spectrum analyzer Measure, visualize and analyze signals . Examine the spectral composition of the waveforms

  4. The Solution

  5. Data Capture Analogical signal  Digital signal

  6. A/D Converter restrictions • The A/D converter ADC0804 • Convert signals with amplitude between 0 and 5 volts. • Addition of a displacement: used to dislocate the signal to the voltage positive axis • Frequency of conversion • 9kHz. • Low-pass filter • Cutoff frequency: 3kHz.

  7. Amplifier • Allows deal with low amplitude signals • Amplification of 6 times • Assist the conversion of the signals • Low amplitude signals make difficult the conversion by the A/D converter.

  8. Routing

  9. The Solution

  10. The Control • Code in SystemC • 541 code lines • Functionalities of a signal and spectrum analyzer • Time base and vertical sensibility adjust • Trigger mode (normal, single e automatic) • Trigger level • Trigger slope • FFT • Use of the Cynthesizer to behavioral synthesis • SystemC • Little time to develop • Some tips to write the code to have a better area and latency • Directives to optimize area and latency without changing the source code

  11. The Cynthesizer • One tool to behavioral synthesis • Behavioral SystemC Synthesizable Verilog RTL • Related to applications guided to algorithms that do not have predominance of conditional entries and exits • Modules in which entries data ate processed by some known algorithm (ex.:FFT)

  12. The Cynthesizer(1/2) Increase the productivity Provide the exploration of many architectures Decreasing the errors

  13. The Cynthesizer (2/2) Same testbench to all level of abstraction Behavioral, SystemC RTL and Verilog RTL Area and latency optimizations without changes in the source code

  14. The Optimizations • Two ways to specified the optimizations: • Directives • Affect some specific part of the code • Command lines • Specified globally just to affect the whole project • Specified to a specific configuration of behavioral synthesis

  15. Architecture Exploration --sched_asap --unroll_loops --sched_aggressive_2 --unroll_loops --dpopt_auto CYN_DEFAULT_INPUT_DELAY CYN_FLATTEN CYN_PROTOCOL

  16. The Control Area Latency

  17. The Solution

  18. Handshake Protocol Interface ready to receive data Data sent by the FPGA Byte sent by the FPGA

  19. The Solution

  20. Device Protection • Restrict the value of the current • Protects the device from short circuit or peak currente • Buffer 74HC244N which only receives one signal (0 to 5 volts) and sent one value that the parallel support.

  21. The Solution

  22. Interface • Code in C++ • 468 code lines • EPP (Enhanced Parallel Port), the type of parallel port mode • Protocol with the FPGA using the parallel port • Easy extension to an others ways of visualization • Possibility to write in an archive

  23. Interface • Automatic mode Volts/div Initiate the capture Mode

  24. Conclusion • Documentation following the ipProcess • Behavioral synthesis makes the work easier! • Optimization without change the source code

  25. Future Works • Change to a better A/D Converter • Other functionalities • Holdoff • Two channels • Design an ASIC AMS

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