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EE 466/586 VLSI Design

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University pande@eecs.wsu.edu. Lecture 6 MOS Inverter Circuits. V. DD. V. V. in. out. C. L. The CMOS Inverter: A First Glance. V. DD. CMOS Inverter. N Well. PMOS. 2 l. Contacts. Out. In. Metal 1.

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EE 466/586 VLSI Design

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  1. EE 466/586VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

  2. Lecture 6 MOS Inverter Circuits

  3. V DD V V in out C L The CMOS Inverter: A First Glance

  4. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND

  5. Two Inverters Share power and ground Abut cells Connect in Metal

  6. Principle of Operation • When the input is at VDD, the NMOS device is conducting while the PMOS device (which has VGS=0 V ) is cut off • Vout is approximately 0 V • When the input is at ground, the NMOS device is cut off while the PMOS device is conducting. Only the small leakage current of the NMOS can flow, so Vout is very close to VDD • VOH = VDD and VOL=0 v • Large noise margin

  7. CMOS Inverter Load Characteristics

  8. CMOS Inverter VTC

  9. CMOS Inverter Characteristics

  10. Region I: n-off, p-lin • The NMOS device is off while the PMOS device is linear. • The output remains at VOH =VDD up to the point when Vin=VTN

  11. Region II: n-sat, p-lin • The NMOS device is on and in saturation, while the PMOS device is still in the linear region since its VDS is relatively small. • IDN(sat)=IDP(lin) • Obtain VIL from here • Follow board notes

  12. Region III: n-sat, p-sat • This involves the nearly vertical segment of the VTC where both transistors are saturated. • Follow board notes • Skewed Inverter

  13. Region IV: n-lin, p-sat • The NMOS device is on and in the linear region since VDS is small • PMOS device is still in saturation • Determine VIH • Follow board notes

  14. Region V: n-lin, p-off • The applied input voltage is above VDD-|VTP|, so the output is now 0 V and will remain that way up to and beyond Vin=VDD.

  15. Pseudo-NMOS Inverter • The saturated-enhancement NMOS load inverter suffers from a lower VOH than the other configurations. • The “linear”-enhancement NMOS load inverter requires two voltage supplies to produce VOH=VDD. • One Advantage • when designing multi-input gates, we only require one load regardless of the number of inputs. • Because of the push-pull arrangement in standard CMOS, it needs roughly twice as many transistors to implement multi -input gates.

  16. Pseudo-NMOS Inverter (Cont’d) • The gate of the PMOS device is connected to ground so that the transistor is always on. • This device is able to pull the output to VDD when the NMOS device is off without the need for additional supplies. • However, it will fight the NMOS transistor when it is on. • it must be sized along with the NMOS device to deliver the desired VOL • Ratioed Structure • When the output is low, power is dissipated in the pseudo-NMOS inverter

  17. VTC of Pseudo-NMOS • VOH = VDD • For VOL • IP( Sat) = IN (Lin) • Follow board notes

  18. Sizing of Inverters • Selecting W/L ratio of the pull-up and pull-down devices • Follow board notes

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