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Superscalar Pipelines

Superscalar Pipelines. Erik Feineis Chris Ielmoni Talal Abdulhaq. Overview. Limitations 1. Problem with Rigid Scalar Pipelines 2. From Scalar to Superscalar Pipelines Organization 1. Parallel 2. Diversified 3. Dynamic Design 1. Instruction Fetching 2. Instruction Decoding

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Superscalar Pipelines

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  1. Superscalar Pipelines Erik Feineis Chris Ielmoni Talal Abdulhaq

  2. Overview • Limitations 1. Problem with Rigid Scalar Pipelines 2. From Scalar to Superscalar Pipelines • Organization 1. Parallel 2. Diversified 3. Dynamic • Design 1. Instruction Fetching 2. Instruction Decoding 3. Instruction Dispatching 4. Instruction Execution 5. Instruction Completion & Retiring

  3. [ Limitations ]Problem with Rigid Scalar Pipelines

  4. [ Limitations ]From Scalar to Superscalar • Parallel Pipelines - Wide pipelines - Advance multiple instructions per cycle • Diversified Pipelines - Multiple functional unit types - Mix of different functional units • Dynamic Pipelines - Out of order execution - Distributed functional units

  5. [ Organization ]Parallel Pipeline

  6. [ Organization (Example) ]Intel Pentium Parallel Pipeline

  7. [ Organization ]Diversified Pipeline

  8. [ Organization ]Dynamic Pipelines

  9. [ Design ]Superscalar Pipeline Design

  10. [ Design ]Instruction Fetching • Objective: Maximize Instruction Throughput • Possible Problems - Misalignment of the fetch group in instruction cache - Branch instructions within the fetch group • Solutions - Static alignment at compile time - Dynamic alignment at run time - Branch prediction and speculation

  11. [ Design ]Instruction Decoding • Primary Tasks - Identify individual instructions - Determine instruction types - Detect inter-instruction dependences • Important Factors - Instruction set architecture - Width of parallel pipeline

  12. [ Design (Example) ]Intel Pentium Pro Fetch/Decode Unit

  13. [ Design ]Instruction Dispatching • Parallel Pipeline - Centralized instruction fetching - Centralized instruction decoding • Diversified Pipeline - Distributed instruction execution

  14. [ Design ]Necessity of Instruction Dispatching

  15. [ Design ]Instruction Execution • Current Trends - More parallelism - Deeper pipes - More diversity • Key Functional Units - Integer units - Floating-point units • Other Functional Units - Branch units - Load/Store units - Specialized units (image, graphic, video, DSP) • Current Challenge - Load/Store parallel processing

  16. [ Design (Examples) ]Specialized Execution Units

  17. [ Design ]Instruction Completion / Retiring • Out-of-order execution - ALU instructions - Load/store instructions • In-order completion/retiring - Precise exception - Memory consistency • Solutions - Reorder buffer (in-order completion) - Store buffer (in-order retiring)

  18. The End

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