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Multi Purpose Digitizer Design Review

Multi Purpose Digitizer Design Review. Paolo Musico and Evaristo Cisbani. MPD design details MPD design status MPD final revision changes Suggestions ???. APV25 BEHAVIOUR. Analog Data (128 bit). HEADER (12bit). Commands: Sync, Calibration, Trigger. Presence Pulses.

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Multi Purpose Digitizer Design Review

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  1. Multi Purpose Digitizer Design Review Paolo Musico and Evaristo Cisbani MPD design details MPD design status MPD final revision changes Suggestions ??? MPD Design Review @ JLAB

  2. APV25 BEHAVIOUR Analog Data (128 bit) HEADER (12bit) Commands: Sync, Calibration, Trigger Presence Pulses MPD Design Review @ JLAB APV25 output signal scope shot

  3. MPD Block Diagram EP1AGX60DF780C6NIN FINAL RELEASE MPD Design Review @ JLAB REMOVED IN FINAL RELEASE SD-CARD INTERFACE IN FINAL RELEASE

  4. MPD 3.0 Implementation JTAG FLASH LEDs SFP Transceiver USB Slave FPGA ETH 10/100 DDR SDRAM DIGITAL I/O VME Interface DC/DC FE DIGITAL Controls MPD Design Review @ JLAB FE ANALOG Inputs ADCs Analog Receivers

  5. System Test Bench in Genova CAENVME-USB Controller MPD MPD Design Review @ JLAB HDMI-A Cable HDMI-B Cable BACKPLANE with 5 APV FrontEnds

  6. ELMA VXS test backplane ELMA p/n: 101VXSM705 MPD Design Review @ JLAB

  7. FPGA details • 16 machines to process APV data • Put data together: event building • Histogramming • Sync machine to check the presence of APVs • Configuration machines: • SPI for ADCs • I2C for ºT, ADC clock delay, APVs parameters • Trigger handling • VME interface MPD Design Review @ JLAB

  8. Single channelprocessor 40 MHz 50 MHz (v 3.0) 100 MHz (v 4.0) Pipelined process Deserialize ADC data(480Mb/s DDR) Identify APV frames Subtracts pedestals Compute common mode noiseand subtract it Apply thresholds MPD Design Review @ JLAB

  9. Event Builder 50 MHz (v 3.0) 100 MHz (v 4.0) Puts together the 16 channels data setadding some info (time, event num)and formatting the event MPD Design Review @ JLAB

  10. Triggering • MPD trigger input can be selected from VXS backplane (2) or front panel LEMO • Trigger command can be sent to APVs in several conditions: • A single command every incoming trigger pulse • Multiple commands (up to 15) every 75 ns • Calibration command followed by one or more trigger commands • Incoming triggers are counted in event builder • Missing frames are counted in channel processor MPD Design Review @ JLAB

  11. Comments Data can be taken out from channel processor “as is” or elaborated Event builder can be enabled or not This implementation has been used for many test beams: all “unfiltered” data have been taken out up to 3 KHz trigger rate (2 MPDs, BLT transfer) MPD is used also by: UVa people, MicroMegas ATLAS guys and OLYMPUS MPD Design Review @ JLAB

  12. Lessons we learned on v 3.0 Care have to be taken in selecting the ADC clock delay respect to the APV clock Same for thresholds to identify logic levels in the APV frames HDMI cables are very good for our purposes Procurement of HDMI-B cable is very difficult Asked for synchronization with external world If we’ll have some “expansions” the board could be adopted in other environments MPD Design Review @ JLAB

  13. What’s new in the 4.0 (final) release:HARDWARE Adoption of HDMI-A for both digital controls and analog data: more space on front panel needed Added front panel clock (40 MHz, LVTTL, 50) USB support removed and Flash memory moved to micro SD-Card interface Adoption of a larger FPGA (20% resources more) Added PMC connectors Software selectable front panel I/O levels MPD Design Review @ JLAB

  14. Micro SD-Card MPD rev 4.0PCB 2 x IN 2 x OUT CLOCK • Ready to go HDMI-A ANALOG Inputs MPD Design Review @ JLAB PMC Connectors

  15. What’s new in the 4.0 (final) release:FPGA (done, functionally simulated) Channel processors and Event Builder clock is now 100 MHz, permitting to have about 40 KHz sustained trigger rate Implemented DDR SDRAM interface and a large data FIFO using itSDRAM can be accessed also through VME for testing purposes Trigger pulse time measurement MPD Design Review @ JLAB

  16. External DDRSDRAM FIFO To Be Improved • 32/64 bit output word • It works in a “ping-pong” way (single port memory) • ≈100 MB/s throughput • Any VME accesspermitted MPD Design Review @ JLAB

  17. What’s new in the 4.0 (final) release:FPGA (to do) • Implement JLAB Multiblock protocol • Check MBLT and dual edges VME transfers (2eVME, 2eSST not supported by our controllers) • Check Jlab DAQ control signals timing: • Clock, Sync, Busy • Trig_in, Trig_out • Statbit_in, Statbit_out • Remote configuration • Use of Eth10/100 and SFP (for future expansions) MPD Design Review @ JLAB

  18. Suggestions, Comments ??? MPD Design Review @ JLAB

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