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Focus group: Statistical synthesis. Not often cited. Often cited. - it pisses my boss off. - worst case is way off. - commercial tools suck. exact SI and IR drop analysis is too complex. - I like to be different. process and environment variation.
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Not often cited Often cited - it pisses my boss off - worst case is way off - commercial tools suck • exact SI and IR drop analysis • is too complex - I like to be different • process and environment • variation • people and circuits need to • play by same rules • economical reasons - it’s none of your business Top reasons to go for statistical
Logic Reference clock - Is analysis needed? - Are we desperate? Objects YES (Yuji, Michel) NO (10% is too much) • How to keep clock as a golden reference? • regular structures (meshes) • common path pessimism removal
Logic Reference clock Main efforts Objects - Is analysis needed? YES (Yuji, Michel) - Are we desperate? NO (10% is too much) • How to keep clock as a golden reference? • regular structures (meshes) • common path pessimism removal
Cadence Magma TI TSMC Break in Design Chain Foundries EDA companies
Best Worst Rule of games I. Corner cases More corner cases (up to 16) Problems: - Worst and best are far
Best Worst Rule of games I. Corner cases More corner cases (up to 16) Problems: - Worst and best are far - Monotonicity??? Assumption: Life in a silicon world is boring
Best Worst Rule of games I. Corner cases More corner cases (up to 16) Problems: - Worst and best are far - Monotonicity??? “Life is beautiful!!!” (Benini) Corner case analysis cannot solve the problem
X * Sigma worst Worst path delay Worst gate delay Rule of games II. Avoiding risk Foundry EDA Company Sigmas are added
Confidence margin worst Optimization room Confidence margin must be big (chips work) But it is fully unknown Statistical analysis and synthesis might help to quantify risk (reduce confidence margin and be structure specific) Statistical analysis might help to trade off confidence margin and yield!
Optimization room Confidence margin Confidence margin must be big (chips work) But it is fully unknown worst Statistical analysis and synthesis might help to quantify risk (reduce confidence margin and be structure specific) Statistical analysis might help to trade off confidence margin and yield! • But testing is a big obstacle!!! • delay fault testing is very difficult • - at-speed testing is very costly(BIST could be an option)
Given: Timing constraints andN• Find: Implementation with DcritwithinN• Optimization room Confidence margin worst Focus of STA
Can I start coding now? Critical path
Can I start coding now? ? Reconvergence needs some care • Numerical computation of a distribution • Approximate convolution (5% accuracy) • Use upper and lower bounds (10% diff. Blaauw’03) Conclusion: we are almost there (check normality assumption, justify approximations)
Today’s vitamins or medicine? • Use of statistical models from foundries • Measuring systematic component of variability (IBM inverter rings) • Exploiting locality in placement of critical parts • Averaging variability by using deeper logic (or balancing logic) • Latch-based designs to relax synchronization constraints
Back to good days: raise the granularity of computation (Bob knows) Tomorrow’s medicine? • Regular non-standard cell design structures (PLA???) Gates dominate wires -> Standard cells are good Submicron paradigm shift: cheap computation vs costly communication • Introducing redundancy • Conscious redundant encoding (a-la asynchronous) for smart • Duplication of critical parts (different implementation) for dummies