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VHDL Synthesis & Simulation: Overview, Concurrent Statements, Sequential Statements

This document provides an overview of VHDL synthesis and simulation, covering topics such as concurrent statements, sequential statements, signal assignment, and resolution function.

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VHDL Synthesis & Simulation: Overview, Concurrent Statements, Sequential Statements

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  1. 未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn

  2. VHDL Synthesis & Simulation

  3. Agenda • Overview • Concurrent Statements • Sequential Statements

  4. Library …;Use …; Entity ……Endentity; Architecture … … …Process …Begin … …End process; … Process …Begin … …End process; … End architecture …; Where? Concurrent Statement Sequential Statement

  5. Agenda • Overview • Concurrent Statements • Signal Assignment • WHEN-ELSE • WITH-SELECT-WHEN • Sequential Statements

  6. C Language void main() { int F;int A = 1;int B = 0;int C = 0;int D = 1; A = B & C; // A = 0 F = A & D; // F = 0, A = 0 } void main() { int F;int A = 1;int B = 0;int C = 0;int D = 1; F = A & D; // F = 1 A = B & C; // A = 0, F = 1 }

  7. Concurrent Statements Example --------------------------------- architecture TS_arch_1 of TS is signal A : std_logic; begin A <= B and C; F <= A and D; end TS_arch_1; library ieee; use ieee.std_logic_1164.all; --------------------------------- entity TS is port (B, C, D : buffer std_logic; F : out std_logic ); end TS; --------------------------------- architecture TS_arch_0 of TS is signal A : std_logic; begin F <= A and D; -- The value of A is not “old” A <= B and C; -- The value of A is updated end TS_arch_0;

  8. Concurrent Statement Property • All the Concurrent Statement is executed in parallel • Concurrent Statement does not care the position within the coding • Concurrent Statement is : OUTPUT depends on INPUT only

  9. Agenda • Overview • Concurrent Statements • Signal Assignment • Delay • Resolution Function • WHEN-ELSE • WITH-SELECT-WHEN • Sequential Statements

  10. Signal Assignment SignalName <= [Options]Expression [afterTimeExpression], Expression [afterTimeExpression], ... ; Delay ? Note: Not in process

  11. Inertial DelayExample A <= B nand C after 0.2 ns; H <= "00", "01" after 10 ns, "10" after 20 ns;

  12. Property of The Inertial Delay • Inertial means that pulses shorter than the delay are ignored. • Example B <= A after 20 ns; (Pulse narrower than 20 ns will not be sent to B) A B 45 ns 4 ns 20 ns

  13. Transport Delay • Transportmeans that the assignment acts as a pure delay line • Example B <= A transportafter 20 ns; (Pulse shorter than 20 ns will also be sent to B) A B 45 ns 4 ns 20 ns

  14. Agenda • Overview • Concurrent Statements • Signal Assignment • Delay • Resolution Function • WHEN-ELSE • WITH-SELECT-WHEN • Sequential Statements

  15. Resolution Function (Example) library ieee;use ieee.std_logic_1164.all;---------------------------------entity SG is port ( A, B : in std_logic; F : out std_logic );end SG;---------------------------------architecture SG_arch of SG is signal A : std_logic;begin F <= A; F <= B; end SG_arch; ?

  16. Resolution Function (std_logic 1) CONSTANT resolution_table : stdlogic_table := ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H - | | -- --------------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); TYPEstd_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; SUBTYPEstd_logicIS resolved std_ulogic;

  17. Resolution Function (std_logic 2) FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result : std_ulogic := 'Z'; -- weakest state default BEGIN IF (s'LENGTH = 1) THEN RETURN s(s'LOW);-- s'LOW is the index of s (can be non-zero) ELSE FOR i IN s'RANGE LOOP result := resolution_table(result, s(i));-- Resolve 2 -- signals each loop END LOOP; END IF; RETURN result; END resolved;

  18. Resolution Function (Example) typelogic_levelis (L, Z, H);typelogic_arrayisarray (integer range <>) oflogic_level; functionresolve_logic (drivers : inlogic_array) returnlogic_level; subtyperesolved_levelisresolve_logiclogic_level; functionresolve_logic (drivers : inlogic_array) returnlogic_level; beginfor index in drivers'range loopif drivers(index) = L thenreturn L;end if;end loop;return H;endresolve_logic;

  19. Agenda • Overview • Concurrent Statements • Signal Assignment • WHEN-ELSE • WITH-SELECT-WHEN • Sequential Statements

  20. WHEN-ELSE SignalName <= Value0 when Condition0 else Value1 when Condition1 else … ValueN-1 when ConditionN-1 else ValueN;

  21. WHEN-ELSE Example mux_out <= 'Z' after 10 ns when en = '0' else in_0 after 10 ns when sel = '0' else in_1 after 10 ns;

  22. Agenda • Overview • Concurrent Statements • Signal Assignment • WHEN-ELSE • WITH-SELECT-WHEN • Sequential Statements

  23. WITH-SELECT-WHEN with Expression select SignalName <= Expression1 [after TimeExpression1] when Choices1, Expression2 [after TimeExpression2] when Choices2, ... ;

  24. WITH-SELECT-WHEN Example WITH sel SELECT q <= a WHEN "00", b WHEN "01", c WHEN "10", d WHEN OTHERS; abcd q sel

  25. Agenda • Overview • Concurrent Statements • Sequential Statements • Process • Latch & Register • Signal Attributes

  26. Library …;Use …; Entity ……Endentity; Architecture … … …Process …Begin … …End process; … Process …Begin … …End process; … End architecture …; Where? Concurrent Statement Sequential Statement

  27. Process (Definition) • Definition Label: process[(SensitivityList)] Declarations... begin SequentialStatements... endprocess [Label]; • Sensitive List • Every process executes once during initialization, before simulation starts. • Process is run when signals in sensitive list changes • Process is running forever if no sensitive list or ‘Wait’ is found.

  28. architecture PS_arch_0 of PS is begin process (A, B, C, D) variable A : std_logic := '0'; begin F <= A and D; A := B and C; end process; end PS_arch_0; --------------------------------- architecture PS_arch_1 of PS is begin process (A, B, C, D) variable A : std_logic := '0'; begin A := B and C; F <= A and D; end process; end PS_arch_1; Process Example (1) library ieee; use ieee.std_logic_1164.all; --------------------------------- entity PS is port ( B, C, D : buffer std_logic; F : out std_logic ); end PS; ---------------------------------

  29. Process Example (2) • All the Process Statement is executed in parallel • Within the Process Statement, the coding is execute in sequential • Process Statement is : OUTPUT depends on INPUT with Sensitivity List to control the event happen entity test1 is Port ( clk, d1, d2 : in bit; q1, q2 : out bit);end test1;architecture test1_body of test1 isbeginProcess (clk, d1)begin if (clk’event and clk = ‘1’) then q1 <= d1; end if;endprocess;Process (clk, d2)beginif (clk’event and clk= ‘1’) then q2 <= d2; end if;endprocess;end test1_body;

  30. architecture VS_arch_0 of VS is signal B : std_logic := '0'; begin process (CLK) begin if rising_edge(CLK) then B <= A; -- F get the changed A one clock F <= B; -- later than B end if; end process; end PS_arch_0; --------------------------------- architecture VS_arch_1 of VS is variable B : std_logic := '0'; begin process (CLK) begin if rising_edge(CLK) then B := A; -- F get the changed A the same F <= B; -- time as Bend if; end process; end VS_arch_1; Delta Delay in Process (1) library ieee; use ieee.std_logic_1164.all; --------------------------------- entity VS is port ( CLK : in std_logic; A : in std_logic; F : out std_logic ); end VS;

  31. Delta Delay in Process (2) A architecture VS_arch_0 of VS is signal B : std_logic := '0'; begin process (CLK) begin if rising_edge(CLK) then B <= A; F <= B;end if; end process; end PS_arch_0; Current B Future B Current F Future F B A D Q CLK D Q CLK F CLK

  32. Delta Delay in Process (3) A architecture VS_arch_1 of VS is variable B : std_logic := '0'; begin process (CLK) begin if rising_edge(CLK) then B := A; F <= B; end if; end process; end VS_arch_1; B Current F Future F B A D Q CLK F CLK

  33. Agenda • Overview • Concurrent Statements • Sequential Statements • Process • Latch & Registers • Signal Attributes

  34. Latch --------------------------------- architecture LT_arch of LT is begin process(CLK, D) begin if CLK = '1' then Q <= D; end if; end process; end LT_arch; library ieee; use ieee.std_logic_1164.all; --------------------------------- entity LT is port ( D, CLK : in bit; Q : out bit ); end LT;

  35. --------------------------------- architecture DFF_arch of DFF is begin process(CLK) begin if CLK’event and CLK = '1' then Q <= D; end if; end process; end DFF_arch; DFF library ieee; use ieee.std_logic_1164.all; --------------------------------- entity DFF is port ( D, CLK : in bit; Q : out bit ); end DFF;

  36. Rising-edge Clock signal A : bit;process (A)begin if A'event and A = ‘1' then ... ... end if; end process; signal A : std_logic; process (A) begin if rising_edge(A) then ... ... end if; end process;

  37. Falling-edge Clock signal A : bit;process (A)begin if A'event and A = '0' then ... ... end if; end process; signal A : std_logic; process (A) begin if falling_edge(A) then ... ... end if; end process;

  38. Asynchronized/Synchronized Set/Reset process (CLK_A, rst)beginif (rst = ‘1’) then ... ... -- Asynchronized resetelsif CLK_A‘event and CLK_A = ’1‘ then ... ...end if;end process; …process (CLK_B)beginif rising_edge(CLK_B) thenif (rst = ‘1’) then … -- Synchronized reset else…end if;end if;end process;

  39. One Clock For Each Process

  40. Wrong Else

  41. A Strange Infinite Loop --******************** entity abcd is end abcd; --************************* architecture abcd_arch of abcd is signal a: bit := '0'; begin process (A) begin a <= not a; end process; end abcd_arch;

  42. Agenda • Overview • Concurrent Statements • Sequential Statements • Process • Latch & Registers • Signal Attributes

  43. Attributes of Signal S is a signal • S’active TRUE if and only if there is a transaction on S in the current delta (The value of S may not change) • S’event TRUE if and only if there is an event on S in the current delta • S’last_active The time since the last transaction on S • S’last_event The time since the last event on S • S’last_value The value of S before the last event

  44. Event & Active

  45. Last_value (1) library ieee; use ieee.std_logic_1164.all; --------------------------------- entity MY_DFF is port(D, CP : in std_logic; Q : out std_logic); end MY_DFF; --------------------------------- architecture MY_DFF_arch of MY_DFF is begin process(CP) begin if (CP'event) and (CP = ‘1') then -- ???? Q <= D; end if; end process; end MY_DFF_arch; 仿真时，CP上取值从‘H’‘1’的改变会被误认为上升沿

  46. Last Value (2) --? Then how about from HL? if (CP'event) and (CP = ‘1') and (CP'last_value = '0') then Q <= D; Therising_edge function in std_1164.vhd also notice this problem FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS -- Exemplar synthesizes this function from the native source code BEGIN RETURN (s'EVENT AND (To_X01(s) = '1') AND (To_X01(s'LAST_VALUE) = '0')); END;

  47. delayed Signal S • S’delayed[(time)] 生成带延迟的信号，time缺省值是0 ns

  48. S’Delayed Example entity and_delay isport(a, b: in std_logic; c: out std_logic);end and_delay;architecture and_delay_arch0 of and_delay is signal tmp_a, tmp_b: std_logic;begintmp_a<= transport a after 5 ns;tmp_b<= transport b after 5 ns;c <=tmp_aandtmp_bafter 10 ns;end and_delay_arch0; --------------------------------------------architecture and_delay_arch1 of and_delay isbeginc <= a’delayed(5 ns) and b’delayed(5 ns) after 10 ns;end and_delay_arch1;

  49. Stable, Quiet & Transaction S is a signal • S’stable [(T)] A signal which is TRUE if and only if no event has occurred on signal S for time T • S’quiet [(T)] A signal which is TRUE if and only if no transaction has occurred on S for time T • S’transaction A signal of type BIT which toggles whenever there is a transaction on S (A signal assignment creates a transaction. A transaction that causes a change in value is an event)

  50. Transaction (Example Code) library ieee; entity DFFs is port(D, CLK : in bit; Q : out bit ); end entity DFFs; architecture DFFs_a of DFFs is begin process(CLK) begin -- if CLK'event and CLK = '1' then if CLK = '1' then Q <= D; end if; end process; end architecture DFFs_a; library ieee; entity Test_DFFs is end Test_DFFs; architecture Test_DFFs_a of Test_DFFs is component DFFs is port(D, CLK : in bit; Q : out bit ); end component DFFs; signal CLK : bit := '0'; signal D, Q : bit; signal CLK_and, SW : bit; signal trans : bit; begin U : DFFs port map(D, CLK_and, Q); SW <= '1', '0' after 44 ns, '1' after 46 ns; CLK_and <= CLK and SW; trans <= CLK_and'transaction; process(CLK) begin CLK <= not CLK after 10 ns; end process; D <= '0', '1' after 15 ns, '0' after 25 ns, '1' after 35 ns; end architecture Test_DFFs_a;

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