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Designing a 4-Bit Shift Register with State Machines<br>

Learn to build a 4-bit parallel input shift register with control inputs 'Load' and 'Shift', utilizing Mealy vs. Moore state machines. Understand state transition diagrams, combinational logic, and synchronous reset for a 4-bit counter. <br>

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Designing a 4-Bit Shift Register with State Machines<br>

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  1. Lab 8 – Sequential Circuits The George Washington UniversitySchool of Engineering and Applied ScienceDepartment of Electrical and Computer Engineering Jason Woytowich November 11, 2005

  2. Schedule • November 11 – Sequential Circuits • November 18 – Review Final Project • November 25 – Thanksgiving, no class • December 2 – Final Project Due

  3. Lab Activity • Build a 4-bit parallel input shift register. • There are two control inputs ‘Load’ and ‘Shift’ • One clock • 4 Parallel inputs and 1 serial output

  4. Design X0 X1 X2 X3 Out Load Shift The clock is not shown

  5. Shift Cell

  6. Shift Register

  7. Testbench

  8. Test Inputs

  9. Test Outputs

  10. State Machines • Completely describe the needed function. • Choose how to implement it. Mealy vs. Moore. • Draw state transition diagrams and assign a representation to the states. • From your diagram create a table of inputs, states, next states, and outputs. • From the table determine the combinational logic needed.

  11. Homework • Build and test a 4-bit counter with synchronous reset and enable count inputs.

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