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Structural and Behavioral Design Style Registers, Counters, and Testbenches

Structural and Behavioral Design Style Registers, Counters, and Testbenches. Resources. Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 4, Registers and Latches Chapter 5, Counters and Simple Arithmetic Functions

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Structural and Behavioral Design Style Registers, Counters, and Testbenches

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  1. Structural and Behavioral Design StyleRegisters, Counters, and Testbenches ECE 449 – Computer Design Lab

  2. Resources • Sundar Rajan, Essential VHDL: RTL Synthesis • Done Right • Chapter 4, Registers and Latches • Chapter 5, Counters and Simple • Arithmetic Functions • Stephen Brown and Zvonko Vranesic, • Fundamentals of Digital Logic with VHDL • Chapter 7, Flip-flops, Registers, Counters, • and a Simple Processor ECE 449 – Computer Design Lab

  3. Structural Design Style ECE 449 – Computer Design Lab

  4. Structural VHDL Major instructions • component instantiation (port map) • generate scheme for component instantiations • (for-generate) • component instantiation with generic • (generic map, port map) ECE 449 – Computer Design Lab

  5. Structural VHDL Major instructions • component instantiation (port map) • generate scheme for component instantiations • (for-generate) • component instantiation with generic • (generic map, port map) ECE 449 – Computer Design Lab

  6. Structural Example: in1 nand_out in2 in1 Component NAND2 Instantiated Four Time ECE 449 – Computer Design Lab

  7. Structural VHDL Major instructions • component instantiation (port map) • generate scheme for component instantiations • (for-generate) • component instantiation with generic • (generic map, port map) ECE 449 – Computer Design Lab

  8. Generate Example Block Diagram xor_tmp(0) xor_tmp(1) xor_tmp(2) xor_tmp(3) xor_tmp(4) xor_tmp(5) xor_tmp(6) xor_tmp(7) ECE 449 – Computer Design Lab

  9. Architecture with for-generate architecture STRUCTURE of PARITY is component XOR2 port( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC ); end component; signal xor_tmp: std_logic_vector (0 to 7); begin xor_tmp(0) <= parity_in(0); G: for i in 0 to 6 generate C: XOR2 port map(A=>xor_tmp(i), B=>parity_in(i+1), Y=>xor_tmp(i+1)); end generate; parity_out <= xor_tmp(7); end STRUCTURE; ECE 449 – Computer Design Lab

  10. Structural VHDL Major instructions • component instantiation (port map) • generate scheme for component instantiations • (for-generate) • component instantiation with generic • (generic map, port map) ECE 449 – Computer Design Lab

  11. N-bit Parity Generator – Entity declaration entity PARITY is generic(N: positive); port( parity_in : in STD_LOGIC_VECTOR(N-1 downto 0); parity_out : out STD_LOGIC ); end PARITY; ECE 449 – Computer Design Lab

  12. N-bit Parity Generator – Architecture architecture STRUCTURE of PARITY is component XOR2 port( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC ); end component; signal xor_tmp: std_logic_vector (0 to N-1); begin xor_tmp(0) <= parity_in(0); G: for i in 0 to N-2 generate C: XOR2 port map(A=>xor_tmp(i), B=>parity_in(i+1), Y=>xor_tmp(i+1)); end generate; parity_out <= xor_tmp(N-1); end STRUCTURE; ECE 449 – Computer Design Lab

  13. Behavioral Design Style ECE 449 – Computer Design Lab

  14. Behavioral VHDL (subset) Major instructions Sequential statements General • process statement (process) • sequential signal assignment () Registers, counters, shift registers, etc. • if-then-else statement State machines • case-when statement Testbenches • loops (for-loop, while-loop) ECE 449 – Computer Design Lab

  15. Anatomy of a Process OPTIONAL [label:] process[(sensitivity list)] [declaration part] begin statement part end process; ECE 449 – Computer Design Lab

  16. What is a PROCESS? • A process is a sequence of instructions referred to as sequential statements. The Keyword PROCESS • A process can be given a unique name using an optional LABEL • This is followed by the keyword PROCESS • The keyword BEGIN is used to indicate the start of the process • All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. • A process must end with the keywords END PROCESS. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST_VECTOR<=“11”; wait for 10 ns; end process; ECE 449 – Computer Design Lab

  17. List of signals to which the process is sensitive. Whenever there is an event on any of the signals in the sensitivity list, the process fires. Every time the process fires, it will run in its entirety. WAIT statements NOT ALLOWED in a processes with SENSITIVITY LIST. label: process (sensitivity list) declaration part begin statement part end process; PROCESS with a SENSITIVITY LIST ECE 449 – Computer Design Lab

  18. Processes in VHDL • Processes Describe Sequential Behavior • Processes in VHDL Are Very Powerful Statements • Allow to define an arbitrary behavior that may be difficult to represent by a real circuit • Not every process can be synthesized • Use Processes with Caution in the Code to Be Synthesized • Use Processes Freely in Testbenches ECE 449 – Computer Design Lab

  19. Use of Processes in the Synthesizable Code ECE 449 – Computer Design Lab

  20. All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputse.g. w, a, b, c All signals which appear in the sensitivity list are inputs e.g. clk Note that not all inputs need to be in the sensitivity list Component Equivalent of a Process clk y w priority a z b c priority: PROCESS (clk) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) = '1' THEN y <= "10" ; ELSIF w(1) = c THEN y <= a and b; ELSE z <= "00" ; END IF ; END PROCESS ; ECE 449 – Computer Design Lab

  21. Registers ECE 449 – Computer Design Lab

  22. Q D Clock D latch Truth table Graphical symbol Q(t+1) Clock D Q(t) – 0 0 1 0 1 1 1 Timing diagram t t t t 1 2 3 4 Clock D Q Time ECE 449 – Computer Design Lab

  23. Q D Clock D flip-flop Truth table Graphical symbol Q(t+1) Clk D 0  0 1  1 – Q(t) 0 Q(t) 1 – Timing diagram t t t t 1 2 3 4 Clock D Q Time ECE 449 – Computer Design Lab

  24. Q D Clock D latch LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ; ARCHITECTURE Behavior OF latch IS BEGIN PROCESS ( D, Clock ) BEGIN IF Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior; ECE 449 – Computer Design Lab

  25. D flip-flop LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_1 OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior_1 ; Q D Clock ECE 449 – Computer Design Lab

  26. D flip-flop LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior_2 OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior_2 ; Q D Clock ECE 449 – Computer Design Lab

  27. D flip-flop with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Q D Clock Resetn ECE 449 – Computer Design Lab

  28. D flip-flop with synchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Resetn = '0' THEN Q <= '0' ; ELSE Q <= D ; END IF ; END PROCESS ; END Behavior ; Q D Clock Resetn ECE 449 – Computer Design Lab

  29. 8 8 Resetn D Q Clock reg8 8-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= "00000000" ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ;` ECE 449 – Computer Design Lab

  30. N N Resetn D Q Clock regn N-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= (OTHERS => '0') ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; ECE 449 – Computer Design Lab

  31. N N N-bit register with enable LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Enable = '1' THEN Q <= D ; END IF ; END IF; END PROCESS ; END Behavior ; Enable Q D Clock regn ECE 449 – Computer Design Lab

  32. Counters ECE 449 – Computer Design Lab

  33. 2 Clear Q upcount Clock 2-bit up-counter with synchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT ( Clear, Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ; END upcount ; ARCHITECTURE Behavior OF upcount IS BEGIN upcount: PROCESS ( Clock ) BEGIN IF (Clock'EVENT AND Clock = '1') THEN IF Clear = '1' THEN Q <= "00" ; ELSE Q <= Q + “01” ; END IF ; END IF; END PROCESS; END Behavior ; ECE 449 – Computer Design Lab

  34. Enable 4 Q Clock upcount Resetn 4-bit up-counter with asynchronous reset (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT ( Clock, Resetn, Enable : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END upcount ; ECE 449 – Computer Design Lab

  35. Enable 4 Q Clock upcount Resetn 4-bit up-counter with asynchronous reset (2) ARCHITECTURE Behavior OF upcount IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN Count <= "0000" ; ELSIF (Clock'EVENT AND Clock = '1') THEN IF Enable = '1' THEN Count <= Count + 1 ; END IF ; END IF ; END PROCESS ; Q <= Count ; END Behavior ; ECE 449 – Computer Design Lab

  36. Shift Registers ECE 449 – Computer Design Lab

  37. Shift register D D D D Q Q Q Q Q(1) Q(0) Q(2) Q(3) Sin Clock Enable ECE 449 – Computer Design Lab

  38. Shift Register With Parallel Load D(0) D D D D Q Q Q Q Load D(3) D(1) D(2) Sin Clock Enable Q(3) Q(2) Q(1) Q(0) ECE 449 – Computer Design Lab

  39. 4 4 Enable D Q Load Sin shift4 Clock 4-bit shift register with parallel load (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shift4 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Enable : IN STD_LOGIC ; Load : IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ; ECE 449 – Computer Design Lab

  40. 4 4 Enable D Q Load Sin shift4 Clock 4-bit shift register with parallel load (2) ARCHITECTURE Behavior_1 OF shift4 IS BEGIN PROCESS (Clock) BEGIN IF Clock'EVENT AND Clock = '1' THEN IF Load = '1' THEN Q <= D ; ELSIF Enable = ‘1’ THEN Q(0) <= Q(1) ; Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= Sin; END IF ; END IF ; END PROCESS ; END Behavior_1 ; ECE 449 – Computer Design Lab

  41. 4 4 Enable D Q Load Sin shift4 Clock 4-bit shift register with parallel load (3) ARCHITECTURE Behavior_2 OF shift4 IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Load = '1' THEN Q <= D ; ELSIF Enable = ‘1’ THEN Q(3) <= Sin; Q(2) <= Q(3) ; Q(1) <= Q(2); Q(0) <= Q(1) ; END IF ; END PROCESS ; END Behavior_2 ; Incorrect!!! ECE 449 – Computer Design Lab

  42. Enable N N D Q Load Sin shiftn Clock N-bit shift register with parallel load (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shiftn IS GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable : IN STD_LOGIC ; Load : IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftn ; ECE 449 – Computer Design Lab

  43. Enable N N D Q Load Sin shiftn Clock N-bit shift register with parallel load (2) ARCHITECTURE Behavior OF shiftn IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Load = '1' THEN Q <= D ; ELSIF Enable = ‘1’ THEN Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ; Q(N-1) <= Sin ; END IF; END IF ; END PROCESS ; END Behavior ; ECE 449 – Computer Design Lab

  44. Input Stimuli Sources in Testbenches ECE 449 – Computer Design Lab

  45. Testbench Block Diagram Design Under Test (DUT) Rule of Thumb: Usually ports from DUT entities are declared as signals within testbench Testbench Environment Stimuli All DUT Inputs Sources of Input Stimuli Simulated Outputs ECE 449 – Computer Design Lab

  46. Testbench Anatomy Entity TB is --TB entity has no ports End TB; Architecture arch_TB of TB is --Local signals and constants component TestComp --All Design Under Test component declarations port ( ); endcomponent; ----------------------------------------------------- for DUT:TestComp useentitywork.TestComp(archName)--Specify entity/arch pair -- (OPTIONAL) begin testSequence: Process --Main test process end process; DUT:TestComp portmap( --Port map all the DUTs ); End arch_TB; ECE 449 – Computer Design Lab

  47. All processes without a sensitivity list fire at least once when the code is simulated. When the process fires, the first statement after the keyword BEGIN is executed. The execution of statements continues sequentially till the last statement in the process. After execution of the last statement, the control is again passed to the beginning of the process. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST_VECTOR<=“11”; wait for 10 ns; end process TESTING; Execution of statements in a PROCESS Order of execution Program control is passed to the first statement after BEGIN ECE 449 – Computer Design Lab

  48. The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns. This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed. This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated. TESTING: process begin TEST_VECTOR<=“00”; wait for 10 ns; TEST_VECTOR<=“01”; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST_VECTOR<=“11”; wait; end process TESTING; PROCESS with a WAIT Statement Order of execution Program execution stops here ECE 449 – Computer Design Lab

  49. Wait for vs. Wait 0 0 1 1 2 2 3 3 Wait for: waveform will keep repeating itself forever … Wait: waveform will keep its state after the last wait instruction. … ECE 449 – Computer Design Lab

  50. Anatomy of a Process [label:] process[(sensitivity list)] [declaration part] begin statement part end process; ECE 449 – Computer Design Lab

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