Digital Logic Design

1. Digital Logic Design University of Palestine Faculty of Engineering and Urban planning Software Engineering Department Lecture 8 of Mohammad Amin KuhailM.Sc. (York, UK) Gate Level Minimization Sunday, 7 October 2007

2. Gate Level Minimization Agenda • Four variable map • Five Variable map • Product of Sums Simplification • Don’t care conditions • NAND and NOR Implementation

3. Four Variable Map Example: Simplify the boolean function

4. Five Variable Map

5. Five Variable Map Example: Map the function

6. Five Variable Map Example: Simplify the Boolean function

7. Product of Sums Simplification Example:

8. Don’t care conditions Definition: • A don’t care condition is a combination of variables whose value is not specified. • It cant be marked with a 1 in the map because it would require the function to be always 1 for such conditions. Likewise, putting a 0 on the square requires the function to be 0. Therefore, an X is used instead.

9. Don’t care conditions Example Simplify the Boolean function Which has the don’t care conditions

10. Don’t care conditions Solution

11. NAND AND NOR IMPLEMENTATION Introduction • Digital circuits are frequently constructed with NAND and NOR gates rather than with AND and OR gates. • NAND and NOR gates are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families.

12. NAND AND NOR IMPLEMENTATION NAND Circuits

13. NAND AND NOR IMPLEMENTATION NAND Circuits Two-Level Implementation

14. NAND AND NOR IMPLEMENTATION NAND Circuits Two-Level Implementation Implement the following function with NAND gates:

15. NAND AND NOR IMPLEMENTATION NAND Circuits Two-Level Implementation

16. NAND AND NOR IMPLEMENTATION NAND Circuits Multi-Level Implementation Implement the following function using NAND gates

17. NAND AND NOR IMPLEMENTATION NAND Circuits Multi-Level Implementation

18. NAND AND NOR IMPLEMENTATION NAND Circuits Multi-Level Implementation Implement the following function using NAND gates

19. NAND AND NOR IMPLEMENTATION NAND Circuits Multi-Level Implementation

20. NAND AND NOR IMPLEMENTATION NOR IMPLEMENTATION

21. NAND AND NOR IMPLEMENTATION NOR IMPLEMENTATION Example: Implement the following function using NOR gates

22. NAND AND NOR IMPLEMENTATION NOR IMPLEMENTATION Example: Implement the following function using NOR gates

23. OTHER TWO LEVEL IMPLEMENTATION AND-OR INVERT

25. OTHER TWO LEVEL IMPLEMENTATION OR-AND INVERT

27. OTHER TWO LEVEL IMPLEMENTATION OR-AND INVERT Implement the following function using NAND-AND, and NoR-oR gates respectively.

29. READING Read: Exclusive OR, P94-99