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A Low-Cost SOC Debug Platform Based on On-Chip Test Architectures Kuen -Jong Lee, Si-Yuan Liang and Alan Su Dept. EE, NCKU ; GUC. Presenter : Shoa-Chieh Hou. SOC Conference, 2009. SOCC 2009. IEEE International . What’s the problem?. Increasing of the chip complexity Bug also increase
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A Low-Cost SOC Debug Platform Based on On-Chip Test ArchitecturesKuen-Jong Lee, Si-Yuan Liang and Alan SuDept. EE, NCKU ; GUC Presenter : Shoa-ChiehHou SOC Conference, 2009. SOCC 2009. IEEE International
What’s the problem? • Increasing of the chip complexity • Bug also increase • Time to market • JTAG is widely used method • ICE • Run stop mechanism • Trace • Usually one port for JTAG in SoC or NoC • Controller needed