1 / 22

EEL 3705 / 3705L Digital Logic Design

This lecture module discusses various methods for coding signed numbers using bits, including sign-magnitude, biased, one's-complement, and two's-complement representations.

robbinsl
Download Presentation

EEL 3705 / 3705L Digital Logic Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. EEL 3705 / 3705LDigital Logic Design Spring 2007Instructor: Dr. Michael Frank Lecture module #10:Binary Representations of Signed Numbers M. Frank, EEL3705 Digital Logic, Fall 2006

  2. Signed Number Representations, Arithmetic, & Overflow Conditions M. Frank, EEL3705 Digital Logic, Fall 2006

  3. Signed Number Representations • In digital systems, we often need to represent signed (positive or negative) numbers. • On paper, a signed base-b number can of course be denoted by just writing down a + or  sign in front of it. • But, how are signed numbers to be coded using bits? • There are many possible methods. We’ll discuss: • Sign-magnitude representations • Biased representations • One’s-complement representations • Two’s-complement representations • This is the one that is most commonly used today in digital systems, due to the simplicity of its implementation M. Frank, EEL3705 Digital Logic, Fall 2006

  4. Sign-Magnitude Representation • To represent signed numbers in the range [2n + 1, 2n  1], we can use one bit for the sign and n bits for the unsigned magnitude (absolute value) of the number. • Most common convention for meaning of sign bit: • 0 = positive, 1 = negative. • Usually, sign bit is written before the magnitude • I.e., next to the most significant bit of the magnitude. • Example: A four-bit sign-magnitude representation of 6 is shown at right • Note that in this system, there are different codes for +0 and 0, even though their values are mathematically the same! • Coping with this makes the design of arithmetic circuits more complicated. Sign=neg. Magni-tude= 6 1110 M. Frank, EEL3705 Digital Logic, Fall 2006

  5. Wheel Diagrams of Unsigned vs. Sign-Magnitude Numbers • Sign-magnitude has more discontinuities, as well as some redundancy and inconsistent ordering… 0 overflowmarker increasingorder 0 increasingorder 1 3 1 000 7 000 111 001 111 001 redundant zero codes 2 2 6 2 110 010 110 010 increasingorder 011 101 011 101 3 1 3 5 100 100 0 4 Four-bit Unsigned Four-bit Sign-Magnitude M. Frank, EEL3705 Digital Logic, Fall 2006

  6. Biased Representations • In a biased or shifted signed number representation, we represent integers in the range [n, p] by using unsigned numbers in the range [0, n+p]. • To convert signed to unsigned: Add n. • To convert unsigned to signed: Subtract n. • When adding biased numbers, we must subtract the bias. • To avoid double-counting it! • Example: • Can represent numbers in the range [8, 7] using the number range [0, 15] by adding 8 to every number. • Numbers in [0, 15] can be represented using 4 bits. M. Frank, EEL3705 Digital Logic, Fall 2006

  7. Wheel Diagrams of Unsigned and Biased Signed Numbers • No extra discontinuities, consistent ordering… • However, arithmetic must still correct for the bias 4 0 3 1 3 000 7 000 111 001 111 001 2 2 6 2 110 010 110 010 increasingorder increasingorder 011 101 011 101 1 1 3 5 100 100 0 4 Four-bit bias-4 signed Four-bit Unsigned M. Frank, EEL3705 Digital Logic, Fall 2006

  8. One’s-Complement Representation • To obtain the representation of x, flip or invert all the bits in the representation of x. • I.e., change all 1’s to 0’s, and 0’s to 1’s. • Like sign-magnitude, encodes the range [2n + 1, +2n  1] in n+1 bits, uses the high-order bit as the sign bit, and has redundant codes for 0. • Unlike sign-magnitude, there is only one discontinuity (instead of 2) when going around the number wheel… • However, the extra 0 code still requires corrections. M. Frank, EEL3705 Digital Logic, Fall 2006

  9. Wheel Diagrams of Unsigned and One’s-Complement Numbers • Discontinuity is only moved, and order is consistent, but there are still two redundant zero codes: 0 0 1 0 1 000 7 000 111 001 111 001 1 2 increasingorder 6 2 110 010 110 010 increasingorder 011 101 011 101 3 2 3 5 100 100 3 Note if we could shiftall of these numbers upby one code, we couldget rid of the −0! 4 Four-bit Unsigned Four-bit One’s-Complement M. Frank, EEL3705 Digital Logic, Fall 2006

  10. Two’s-Complement Representation • Represent x as • One’s-complement of x, plus another 1 added in • Thus the name “two’s complement.” • The first bit is still the sign bit… • Or, you can also think of it as a negative digit, representing the “2n1’s” position in the number. • E.g., the high bit in a 4-bit number is the 8’s position (instead of the 8’s position). • Big advantage of two’s complement: • The addition circuit is the same as for unsigned! • Only the overflow conditions are different. M. Frank, EEL3705 Digital Logic, Fall 2006

  11. Wheel Diagrams of Unsigned and Two’s-Complement Signed Numbers • Only one discontinuity, no redundant codes! • No need to correct for biases! 0 0 1 1 1 000 7 000 111 001 111 001 2 2 increasingorder 6 2 110 010 110 010 increasingorder 011 101 011 101 3 3 3 5 100 100 4 4 Four-bit Unsigned Four-bit Two’s-Complement M. Frank, EEL3705 Digital Logic, Fall 2006

  12. Overflow Conditions for Two’s Complement • Overflow occurs when we cross the boundary separating the most positive number, 01111… from the most negative number, 10000… • When this happens, there is a carry from the second-most-significant bit position (bit #n2) to the most significant bit position (bit #n1). • Doing this, by itself, is incorrect, since the most significant bit position has the opposite sign. • However, if there is also a carry out of the most significant bit position, then it’s OK… • In this case, we’re just going through the continuous range from the negative numbers close to zero, which begin with 111… to the positive numbers close to zero, which begin with 000… M. Frank, EEL3705 Digital Logic, Fall 2006

  13. Signed Overflow Example • Is there an overflow when adding the bit patterns 110 and 011 in three-bit, signed two’s-complement arithmetic? • Method 1: Does sum fit in range? 110  2, 011  3, 2+3 = +1  001. Yes; no overflow. • Method 2: Perform unsigned add.Carries into and out of high bitposition are the same  no signed overflow. 1 1 110+ 011 1001 M. Frank, EEL3705 Digital Logic, Fall 2006

  14. Subtraction in Two’s Complement • To perform the subtraction x y in n bits using two’s complement arithmetic, • Just compute z, the two’s complement of y, using z = y = y + 1. • Or, shortcut method: Flip all bits that are to the left of the rightmost 1. • Then, simply add x + z, • and truncate the result to n bits. • If there is no signed overflow, • the result will be correct. • Exception: If y = −2n−1, then z = y + 1 = y, not −y! • E.g., in 8 bits, −128 = 1000,0000; its two’s complement is the same; and thus its negative +128 is not representable. M. Frank, EEL3705 Digital Logic, Fall 2006

  15. Two’s-Complement Subtraction Example • Compute the subtraction 13 using two’s complement arithmetic in three bits. • 1 = 0012 • 3 = 0112 • 3 = 1002 (one’s complement) • 3 = 3+1 = 1012 (two’s complement) • 1  3 = 1 + (3) = 1002 + 1012 = 1102 • Bits in and out of high bit match; no signed overflow • 1102 = 4 + 2 = 2 (correct result) 1 0 0 001+ 101 110 M. Frank, EEL3705 Digital Logic, Fall 2006

  16. Two’s Complement Subtraction: Another Practice Problem • Perform this subtraction: • –3 – (–6) in 4-bit two’s complement (is there an overflow?) • +3 = 0011, ~3 = 1100, ~3+1 = 1101 = -3 • +6 = 0110, ~6 = 1001, ~6+1 = 1010 = -6 • -6 = 1010, ~(-6) = 0101, ~(-6)+1 = 0110 = +6 • -3 = 1101+6 = + 0110 1|0011 -> +3 M. Frank, EEL3705 Digital Logic, Fall 2006

  17. Exact Two’s Complement Addition/Subtraction, & Sign Extension • Suppose you want to add any two n-bit signed numbers and get the correct (n+1)-bit result. • E.g., given 3+(−2) in 8 bits, what’s their 9-bit sum? • 0000,00112 + 1111,11102 = _,_ _ _ _,_ _ _ _2 ? • It turns out that to simply keep around all 9 bits of the unsigned sum will not work in general. • Reason: Carry into position n−1is positive, bits in that position are −ive. • Solution: First sign-extend both addends to their (n+1)-bit-long equivalents, • Copy high bit into next position to the left. • then add, and truncate result to n+1 bits (ignoring any overflow). • This result will always be correct! 0000,0011 = +3 + 1111,1110 = −2 1,0000,0001 = −255! 0,0000,0011 = +3 + 1,1111,1110 = −2 10,0000,0001 = +1! M. Frank, EEL3705 Digital Logic, Fall 2006

  18. Another Method for Detecting Two’s Complement Overflow • When adding two n-bit signed (two’s complement) numbers in-place to get an n-bit signed result, • There is a signed overflow if, and only if, • Both addends have the same sign, • and the sum has a different sign. • That is, if we got pos+pos = neg, or neg+neg = pos, then the result is (obviously!) incorrect. • All signed overflows are of this sort (sign error in result). • Simple detection formula: • This method doesn’t require looking at the carry bits, so it can operate externally to the adder itself. M. Frank, EEL3705 Digital Logic, Fall 2006

  19. Example: 8-bit signed adder/subtracterwith signed/unsigned overflow detection • Note that this design lets us use any 8-bit to 9-bit unsigned adder, without opening it up. M. Frank, EEL3705 Digital Logic, Fall 2006

  20. Radix Complement (Optional Topic) • A generalization of two’s complement to bases other than 2. • In any base b, the radix complement [N]b of an n-digit number Nb is defined as [N]b = bn− Nb. • The normal unsigned representation of [N]b is then the signed representation of −Nb. • Radix complement is the same as two’s complement when b=2. • Example: −00012 → [0001]2 = 24 − 1 = 100002 − 1 = 11112. • You’ll rarely encounter this concept for b2. M. Frank, EEL3705 Digital Logic, Fall 2006

  21. Radix Complement Example for b2 • Compute the three’s complement of the number 01223 (= 1710). • The number of digits in 01223 is n=4. • [0122]3 = 34− 1223 = 8110 − 1710 = 6410 = 21013. • We could obtain the same result by the idea of “complementing the digits and adding 1” • where digit complements are pairs of digit values that sum to the max digit value, here b−1 = 2. In base 3, 0 and 2 are digit complements, and 1 is its own digit complement. • [0122]3 = ~01223 + 1 = 21003 + 1 = 21013. • The two methods are equivalent in any base b, because ((b−1)(b−1)…(b−1))b + 1 = 100…0b = bn. n n M. Frank, EEL3705 Digital Logic, Fall 2006

  22. Diminished Radix Complement • This is just the radix complement minus 1. • In the book’s notation, [N]b−1 = [N]b − 1. • This is the same as just taking the digit complement of all digits. • where, in base b, the digit complement of any digit d is given by ~d = (b−1)−d. • In base b=2, the digit complement of a digit d is given by 1−d, which is another reason that we call the digit complement in base 2 the “one’s complement”. M. Frank, EEL3705 Digital Logic, Fall 2006

More Related