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MAVEN Digital/FPGA Peer Review DCB (Board and FPGA) May 12, 2010

This peer review focuses on the FPGA subsystems, basic subsystems, and specifications of the MAVEN Digital Control Board (DCB). It includes details on the board, FPGA, interfaces, memory, power, and more.

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MAVEN Digital/FPGA Peer Review DCB (Board and FPGA) May 12, 2010

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  1. MAVEN Digital/FPGA Peer Review DCB (Board and FPGA) May 12, 2010 D. Gordon

  2. DCB in the PFDPU

  3. DCB Block Diagram

  4. DCB Basic Subsystems • Basic Subsystems • C&DH Interface • Commands arrive via UART (57.6Kbaud) • Telemetry transmitted via UART (57.6Kbaud) • Discrete Commands arrive via Optocouplers • S/C RESET, SC CLK1HZ, SIDESELECT • Memory • Boot ROM, EEPROM, CPU SRAM and Instrument SRAM • FLASH – 8Gbytes in two separately powered 4Gbyte modules • Instrument Interface - Mode Setup and Data Ingest • Instrument initialization parameters as outlined in ICDs

  5. DCB Basic Subsystems (continued) Basic subsystems (continued) Timekeeping Internal 16.78 MHz (224 Hz) system Provides instrument timebase (Sample Time) Logic timestamps S/C CLK1Hz with respect to Sample Time Generates CPU Interrupts and Watchdog Timer Reset Provides Instrument DMA Buffer Swap “ticks” Housekeeping REG forwards analog signal to DCB based ADC (1604) FSW controls address and enables to REG based analog multiplexors FSW samples data at regular intervals

  6. DCB FPGA DCB – Data Controller Board DCB FPGA is the RTAX2000S-1CG624E Advanced testing phase: AX2000-1CG624 (same footprint – fused device) Initial Development phase: A3PE3000-FG324 (FLASH device) via the “FPGA Daughter Board” 10K R-Cells, 21K C-Cells, 36Kbytes Internal SRAM System Clock = 16.78MHz – independent onboard oscillator Estimated Power: 500mW (170mW I/O; 330mW Core) typical 850mW (180mW I/O; 670mW Core) at 70C Utilization Estimate ~75% modules; 190 I/Os (constrained by FPGA daughter card to ~200 max) Block RAM: 4 blocks for S/C CMD IF memory and 1 block for InstCmdFIFO (out of 64 block total) (error correction will increase utilization)

  7. DCB FPGA Subsystems Coldfire V1 CPU Core 32-bit microprocessor core with 24-bit address bus IP Core, delivered in January, supported by IPExtreme CPU Bus Interface AMBA 2 AHB Unified instruction/data bus decoded by FPGA Interfaces with internal Register bank and MBUS for external memory and peripherals Registers I/O Bank and Actuator Control MBUS Control Spacecraft Interface Commands via Dual Port Memory Telemetry via DMA (8 channels)

  8. DCB FPGA Subsystems (continued) Instrument CDI Commands via FIFO 256 Word Instrument FIFO provides 6.8 ms of buffer (one FIFO shared between the 7 instruments) Message Intake via DMA Each Instrument allocated its own double-buffered segment within SRAM Buffers are configured to swap either every second, every 2 seconds or every 4 seconds (synchronous to the instrument acquisition cycles) Timekeeping Sample Time available to FSW via the Register I/F Timestamped S/C 1Hz via the Register I/F F0 Command generated and forwarded to Instruments via CDI Interface

  9. DCB FPGA Subsystems (continued) REG (LVPS) Interface Instrument Power Switches Overcurrent control handled by the logic Inrush guardband when switch is activated (10ms to 100ms) Override possible via Command I/F Overcurrent status from LVPS per instrument Switch is turned off if the Inrush Guardband and the Override are both deasserted when the Overcurrent signal is asserted Actuator Control (Switches reside on the REGs board) Time of activation is settable via Register Interface From 0.625 seconds to 16 seconds with a “FORCEON” option Addressed actuator must be armed and fired Digital status is available via optocoupled feedback (for all actuators except EUV)

  10. DCB FPGA Subsystems (continued) FLASH Memory Control Addresses two stacked memory modules (3D-Plus MMFN08408808S-F-1S) Each module is 2G x 8, using eight MICRON 256M x 8 FLASH components Each 3D-Plus FLASH Module is independently isolated -- switchable power Defaults to off at power on; turns off with watchdog reset Devices are kept off during periods of inactivity Optimize TID lifetime and minimize power drain Reset command issued at the beginning of each DMA Transfer Minimizes impact of Single Event Functional Interrupts (SEFI) Error correction option – Hamming code Correction applied to 512 byte segments for DMA writes Error detection/correction during readout DMA mode: transfers data to/from SRAM CPU sets up DMA; handles buffer allocation and bad block management Processor mode: CPU can read/write as a device in memory mapped mode

  11. Detailed Design Links Initial board Placement Sketch ..\..\PFDPU\PCBLayout\dcbpmtPrelim07may10.pdf Schematics for DCB and FLASH Daughter Card ..\..\PFDPU\Sch\MAVENDPU.DSN ..\..\PFDPU\Sch\FLASHDCARD.DSN MAVEN PFP Block Diagram ..\..\Systems\MAVEN_PF_SYS_013D_Harnessing.pdf Specification for PFDPU ..\..\PFDPU\Spec\MAVEN_PF_PFDPU_001D_DCB_Specification.doc Real Estate/Power ..\..\PFDPU\Spec\DCBest.xls

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