80 likes | 196 Views
Doing the VCS Assignment. Download the Calc1 code Unzip/Uncompress it Go into the directory with the verilog code. There are several verilog files including: calc1_top.v - the main design file testbench.v - contains the stimulus, instantiates the design You will simulate testbench.v
E N D
Doing the VCS Assignment Download the Calc1 code Unzip/Uncompress it Go into the directory with the verilog code There are several verilog files including: calc1_top.v - the main design file testbench.v - contains the stimulus, instantiates the design You will simulate testbench.v This will force the compilation/simulation of all other blocks
Running VCS • Type vcs -RI testbench.v • The Interactive Window appears
Waveform Window • Open the Waveform Window • Need to select the signals you want to see, use Hierarchy Window
Hierarchy Window • Select the bigtest module to see its signals • Drag-and-drop the signals into the Waveform Window
Waveform Window with Signals • The signals are on display, but they are blank
Execute Simulation • Simulate by selecting Continue • Printed results are shown in top pane
Waveforms Results • Waveform Window is updated with results • Zoom out and scroll over time