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Lecture 9 Registers, Counters and Shifters

Lecture 9 Registers, Counters and Shifters. Hai Zhou ECE 303 Advanced Digital Design Spring 2002. Outline. Registers Register Files Counters Designs of Counters with various FFs Shifters READING: Katz 7.1, 7.2, 7.4, 7.5, 4.7 Dewey 10.2, 10.3, 10.4, Hennessy-Patterson B26.

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Lecture 9 Registers, Counters and Shifters

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  1. Lecture 9 Registers, Counters and Shifters Hai Zhou ECE 303 Advanced Digital Design Spring 2002 ECE C03 Lecture 9

  2. Outline • Registers • Register Files • Counters • Designs of Counters with various FFs • Shifters • READING: Katz 7.1, 7.2, 7.4, 7.5, 4.7 Dewey 10.2, 10.3, 10.4, Hennessy-Patterson B26 ECE C03 Lecture 9

  3. Building Complex Memory Elements • Flipflops: most primitive "packaged" sequential circuits • More complex sequential building blocks: Storage registers, Shift registers, Counters Available as components in the TTL Catalog • How to represent and design simple sequential circuits: counters • Problems and pitfalls when working with counters: Start-up States Asynchronous vs. Synchronous logic ECE C03 Lecture 9

  4. Registers • Storage unit. Can hold an n-bit value • Composed of a group of n flip-flops • Each flip-flop stores 1 bit of information • Normally use D flip-flops D Q Dff clk D Q Dff clk D Q Dff clk D Q Dff clk ECE C03 Lecture 9

  5. Controlled Register D Q Dff clk D Q Dff clk D Q Dff clk D Q Dff clk ECE C03 Lecture 9

  6. Registers Group of storage elements read/written as a unit 4-bit register constructed from 4 D FFs Shared clock and clear lines Schematic Shape TTL 74171 Quad D-type FF with Clear (Small numbers represent pin #s on package) ECE C03 Lecture 9

  7. Shift Registers Storage + ability to circulate data among storage elements \Reset Shift Direction J K Q Q J K Q Q Q Q J K Q Q J K Shift \Reset Shift Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal Wrap around from rightmost element to leftmost element Q1 Q2 Q3 Q4 Master Slave FFs: sample inputs while clock is high; change outputs on falling edge ECE C03 Lecture 9

  8. Shift Registers I/O Serial vs. Parallel Inputs Serial vs. Parallel Outputs Shift Direction: Left vs. Right Serial Inputs: LSI, RSI Parallel Inputs: D, C, B, A Parallel Outputs: QD, QC, QB, QA Clear Signal Positive Edge Triggered Devices S1,S0 determine the shift function S1 = 1, S0 = 1: Load on rising clk edge synchronous load S1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element D S1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element A S1 = 0, S0 = 0: hold state Multiplexing logic on input to each FF! QD QC QB QA 74194 4-bit Universal Shift Register Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications ECE C03 Lecture 9

  9. Application of Shift Registers Parallel to Serial Conversion Sender Receiver S1 S1 194 194 S0 S0 LSI LSI D D7 D D7 QD QD C D6 C D6 QC QC B D5 B D5 QB QB D4 A D4 A QA QA RSI RSI Clock CLK CLK Parallel Inputs Parallel Outputs CLR CLR S1 S1 194 194 S0 S0 LSI LSI D D3 D D3 QD QD C D2 C D2 QC QC B D1 B D1 QB QB D0 A D0 A QA QA RSI RSI CLK CLK CLR CLR Serial transmission ECE C03 Lecture 9

  10. Counters Proceed through a well-defined sequence of states in response to count signal 3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ... 3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ... Binary vs. BCD vs. Gray Code Counters A counter is a "degenerate" finite state machine/sequential circuit where the state is the only output ECE C03 Lecture 9

  11. Counter Design Procedure This procedure can be generalized to implement ANY finite state machine Counters are a very simple way to start: no decisions on what state to advance to next current state is the output Example: 3-bit Binary Upcounter Present State Next State Flipflop Inputs 000 Decide to implement with Toggle Flipflops What inputs must be presented to the T FFs to get them to change to the desired state bit? This is called "Remapping the Next State Function" C B A C+ B+ A+ TC TB TA 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1 001 State Transition Table Flipflop Input Table ECE C03 Lecture 9

  12. Example Design of Counter K-maps for Toggle Inputs: Resulting Logic Circuit: CB 11 A 00 01 10 0 1 TA = CB 11 A 00 01 10 0 1 TB = CB 11 A 00 01 10 0 1 ECE C03 Lecture 9 TC =

  13. Resultant Circuit for Counter Resulting Logic Circuit: K-maps for Toggle Inputs: + QA QB QC S S S Q Q Q T T T CLK CLK Q CLK Q Q R R R \Reset Count Timing Diagram: ECE C03 Lecture 9

  14. More Complex Counter Design Step 1: Derive the State Transition Diagram Count sequence: 000, 010, 011, 101, 110 Present State Next State Step 2: State Transition Table 0 0 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 0 ECE C03 Lecture 9

  15. Complex Counter Design (Contd) Step 1: Derive the State Transition Diagram Count sequence: 000, 010, 011, 101, 110 Present State Next State Step 2: State Transition Table 0 0 0 0 1 0 0 0 1 X X X 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 X X X 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 X X X Note the Don't Care conditions ECE C03 Lecture 9

  16. Counter Design (Contd) Step 3: K-Maps for Next State Functions CB CB 11 A 00 01 10 11 A 00 01 10 0 0 1 1 C+ = B+ = CB 11 A 00 01 10 0 1 A+ = ECE C03 Lecture 9

  17. Counter Design (contd) Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions Present State Toggle Inputs C B A TC TB TA Q Q+ T 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 0 0 1 X X X 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 X X X 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 X X X Toggle Excitation Table Remapped Next State Functions ECE C03 Lecture 9

  18. Resultant Counter Design Remapped K-Maps CB CB 11 A 00 01 10 11 A 00 01 10 0 0 1 1 TC TB CB 11 A 00 01 10 0 1 TA TC = A C + A C = A xor C TB = A + B + C TA = A B C + B C ECE C03 Lecture 9

  19. Resultant Circuit for Complex Counter Resulting Logic: 5 Gates 13 Input Literals + Flipflop connections TB B TA A TC C S S S Q Q T Q T T Q Q Q CLK CLK CLK \C \B \A R R R Count \Reset A C \A B C \B C TC TA A \B C TB Timing Waveform: ECE C03 Lecture 9

  20. Implementing Counters with Different FFs • Different counters can be implemented best with different FFs • Steps in building a counter • Build state diagram • Build state transition table • Build next state K-map • Implementing the next state function with different FFs • Toggle flip flops best for binary counters • Existing CAD software for finite state machines favor D FFs ECE C03 Lecture 9

  21. Implementing 5-state counter with RS FFs Continuing with the 000, 010, 011, 101, 110, 000, ... counter example Rmepped next state Present State Next State Q Q+ R S 0 0 X 0 0 1 0 1 1 0 1 0 1 1 0 X RC SC RB SB RA SA 0 0 0 0 1 0 X 0 0 1 X 0 0 0 1 X X X X X X X X X 0 1 0 0 1 1 X 0 0 X 0 1 0 1 1 1 0 1 0 1 1 0 0 X 1 0 0 X X X X X X X X X 1 0 1 1 1 0 0 X 0 1 1 0 1 1 0 0 0 0 1 0 1 0 X 0 1 1 1 X X X X X X X X X Q+ = S + R Q RS Exitation Table Remapped Next State Functions ECE C03 Lecture 9

  22. Implementation with RS FFs CB CB 11 11 A 00 01 10 A 00 01 10 0 0 1 1 RC SC CB CB 11 11 A 00 01 10 A 00 01 10 0 0 1 1 RB SB CB CB 11 11 A 00 01 10 A 00 01 10 0 0 1 1 RA SA RS FFs Continued 0 0 0 X X 1 X X X X 1 X X 0 X 0 RC = A SC = A RB = A B + B C SB = B RA = C SA = B C 0 0 1 X X 1 X 0 1 X 0 X X 0 X 1 X 0 X X X 0 X 1 0 1 0 X X X X 0 ECE C03 Lecture 9

  23. Implementation With RS FFs \ A \ B \ C \ B C B A RB R C R Q R Q Q CLK CLK CLK Q A S Q Q S SA S \A Count A B RB SA C B \C Resulting Logic Level Implementation: 3 Gates, 11 Input Literals + Flipflop connections ECE C03 Lecture 9

  24. Implementing with JK FFs Continuing with the 000, 010, 011, 101, 110, 000, ... counter example Rmepped next state Present State Next State Q Q+ J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 JC KC JB KB JA KA 0 0 0 0 1 0 0 X 1 X 0 X 0 0 1 X X X X X X X X X 0 1 0 0 1 1 0 X X 0 1 X 0 1 1 1 0 1 1 X X 1 X 0 1 0 0 X X X X X X X X X 1 0 1 1 1 0 X 0 1 X X 1 1 1 0 0 0 0 X 1 X 1 0 X 1 1 1 X X X X X X X X X Q+ = S + R Q RS Exitation Table Remapped Next State Functions ECE C03 Lecture 9

  25. Implementation with JK FFs CB CB 11 11 A 00 01 10 A 00 01 10 0 0 1 1 JC = A KC = A/ JB = 1 KB = A + C JA = B C/ KA = C JC KC CB CB 11 11 A 00 01 10 A 00 01 10 0 0 1 1 JB KB CB CB 11 11 A 00 01 10 A 00 01 10 0 0 1 1 JA KA ECE C03 Lecture 9

  26. Implementation with JK FFs \ A \ C \ B \ A \ C + C B A A J Q J Q JA J Q CLK CLK CLK C K Q KB K Q K Q Count A B JA KB C Resulting Logic Level Implementation: 2 Gates, 10 Input Literals + Flipflop Connections ECE C03 Lecture 9

  27. Implementation with D FFs Simplest Design Procedure: No remapping needed! DC = A DB = A C + B DA = B C Resulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections ECE C03 Lecture 9

  28. Comparison with Different FF Types • T FFs well suited for straightforward binary counters But yielded worst gate and literal count for this example! • No reason to choose R-S over J-K FFs: it is a proper subset of J-K R-S FFs don't really exist anyway J-K FFs yielded lowest gate count Tend to yield best choice for packaged logic where gate count is key • D FFs yield simplest design procedure Best literal count D storage devices very transistor efficient in VLSI Best choice where area/literal count is the key ECE C03 Lecture 9

  29. Summary • Registers • Register Files • Counters • Designs of Counters with various FFs • NEXT LECTURE: Memory Design • READING: Katz 7.6 ECE C03 Lecture 9

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