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Ciclo 6

MEM/WB. ID/EX. EX/MEM. IF/ID. Adder. 4. Address. ALU. Ciclo 6. Determinou o endereço de A. A. 06 - add r1,r2,r3. 04 - sub r8,r9,r10. 03 - or r5,r6,r7. 05 - xor r11,r12,r13. 02 - and r2,r3,r4. Next PC. MUX. Next SEQ PC. Next SEQ PC. Zero?. RS1. Reg File. MUX. Memory. RS2.

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Ciclo 6

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  1. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 6 Determinou o endereço de A A 06 - add r1,r2,r3 04 - sub r8,r9,r10 03 - or r5,r6,r7 05 - xor r11,r12,r13 02 - and r2,r3,r4 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  2. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 7 Determinou o endereço de A A 07 - and r2,r3,r4 06 - add r1,r2,r3 04 - sub r8,r9,r10 03 - or r5,r6,r7 05 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  3. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 8 Determinou o endereço de A A 04 - sub r8,r9,r10 08 - or r5,r6,r7 07 - and r2,r3,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  4. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 9 Determinou o endereço de A A 08 - or r5,r6,r7 07 - and r2,r3,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 09 - sub r8,r9,r10 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  5. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 10 Determinou o endereço de A A 08 - or r5,r6,r7 07 - and r2,r3,r4 06 - add r1,r2,r3 09 - sub r8,r9,r10 10 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  6. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 6 Com dependência de dados Determinou o endereço de A A 06 - add r1,r2,r3 04 - sub r8,r9,r10 03 - or r5,r6,r7 05 - xor r11,r12,r13 02 - and r2,r3,r4 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  7. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 7 Determinou o endereço de A A 07 - and r2,r1,r4 06 - add r1,r2,r3 04 - sub r8,r9,r10 03 - or r5,r6,r7 05 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  8. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 8 Determinou o endereço de A A 04 - sub r8,r9,r10 08 - or r5,r6,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  9. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 9 Determinou o endereço de A A 08 - or r5,r6,r7 07 - and r2,r1,r4 bolha 06 - add r1,r2,r3 05 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  10. bolha bolha MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 10 Determinou o endereço de A A 08 - or r5,r6,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  11. bolha bolha bolha MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 11 Determinou o endereço de A A 08 - or r5,r6,r7 07 - and r2,r1,r4 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  12. bolha bolha MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 12 Determinou o endereço de A A 08 - or r5,r6,r7 07 - and r2,r1,r4 09 - sub r8,r9,r10 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  13. bolha MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 13 Determinou o endereço de A A 08 - or r5,r6,r7 07 - and r2,r3,r4 09 - sub r8,r9,r10 10 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  14. ALU Forwarding ID/EX EX/MEM MEM/WR NextPC mux Registers Data Memory mux mux Immediate CS252-s06, Lec 02-intro

  15. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 6 Com forwarding Determinou o endereço de A A 06 - add r1,r2,r3 04 - sub r8,r9,r10 03 - or r5,r6,r7 05 - xor r11,r12,r13 02 - and r2,r3,r4 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  16. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 7 Determinou o endereço de A A 07 - and r2,r1,r4 06 - add r1,r2,r3 04 - sub r8,r9,r10 03 - or r5,r6,r7 05 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  17. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Vai ler o valor errado no fim do ciclo Ciclo 8 Determinou o endereço de A A 04 - sub r8,r9,r10 08 - or r5,r1,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  18. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Vai ler o valor errado no fim do ciclo Usa o valor correto via forwarding Ciclo 9 Determinou o endereço de A A 08 - or r5,r1,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 09 - sub r8,r1,r10 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  19. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Vai ler o valor certo no fim do ciclo Usa o valor correto via forwarding Ciclo 10 Determinou o endereço de A A 08 - or r5,r1,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 09 - sub r8,r1,r10 10 - xor r11,r1,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 WB Data Imm RD RD RD Registradores feitos com FFs tipo D acionados por nível CS252-s06, Lec 02-intro

  20. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 8 Dependência verdadeira - LW Determinou o endereço de A A 04 - sub r8,r9,r10 08 - or r5,r6,r7 07 - and r2,r1,r4 06 - lw r1,0(r3) 05 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – lw r1,0(r3) Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  21. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 9 Determinou o endereço de A A 08 - or r5,r6,r7 07 - and r2,r1,r4 bolha 06 - lw r1,0(r3) 05 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – lw r1,0(r3) Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  22. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 10 Determinou o endereço de A A 08 - or r5,r6,r7 09 - sub r8,r1,r10 bolha 06 - lw r1,0(r3) 07 - and r2,r1,r4 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – lw r1,0(r3) Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  23. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 6 Desvios condicionais – bolhas para trás Determinou o endereço de A A 06 - beqz r1, i10 04 - sub r8,r9,r10 03 - or r5,r6,r7 05 - xor r11,r12,r13 02 - and r2,r3,r4 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – beqz r1, i10 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  24. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 7 Determinou o endereço de A A 07 - and r2,r3,r4 04 - sub r8,r9,r10 03 - or r5,r6,r7 05 - xor r11,r12,r13 06 - beqz r1, i10 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – beqz r1, i10 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  25. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 8 Determinou o endereço de A A 04 - sub r8,r9,r10 08 - or r5,r6,r7 07 - and r2,r3,r4 05 - xor r11,r12,r13 06 - beqz r1, i10 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – beqz r1, i10 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  26. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Ciclo 9 Determinou o endereço de A A anulada 08 - or r5,r6,r7 anulada 07 - and r2,r3,r4 06 - beqz r1, i10 05 - xor r11,r12,r13 10 - xor r11,r12,r13 Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – beqz r1, i10 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 WB Data Imm RD RD RD CS252-s06, Lec 02-intro

  27. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Pipeline melhorado Instruction Fetch Execute Addr. Calc Memory Access Instr. Decode Reg. Fetch Write Back Next SEQ PC Next PC MUX Adder Zero? RS1 Reg File Memory RS2 Data Memory MUX MUX Sign Extend WB Data Imm RD RD RD • Perda de apenas um ciclo se o desvio for tomado CS252-s06, Lec 02-intro

  28. Four Branch Hazard Alternatives #1: Stall until branch direction is clear #2: Predict Branch Not Taken • Execute successor instructions in sequence • “Squash” instructions in pipeline if branch actually taken • Advantage of late pipeline state update • 47% MIPS branches not taken on average • PC+4 already calculated, so use it to get next instruction #3: Predict Branch Taken • 53% MIPS branches taken on average • But haven’t calculated branch target address in MIPS • MIPS still incurs 1 cycle branch penalty • Other machines: branch target known before outcome CS252-s06, Lec 02-intro

  29. Four Branch Hazard Alternatives #4: Delayed Branch • Define branch to take place AFTER a following instruction branch instruction sequential successor1 sequential successor2 ........ sequential successorn branch target if taken • 1 slot delay allows proper decision and branch target address in 5 stage pipeline • MIPS uses this Branch delay of length n CS252-s06, Lec 02-intro

  30. becomes becomes becomes if $2=0 then add $1,$2,$3 if $1=0 then add $1,$2,$3 sub $4,$5,$6 add $1,$2,$3 if $1=0 then sub $4,$5,$6 Escalonando Branch Delay Slots A. From before branch B. From branch target C. From fall through add $1,$2,$3 if $1=0 then add $1,$2,$3 if $2=0 then • A é a melhor escolha, pois enche o slot e reduz a contagem de instruções (CI) • Em B, a instrução sub pode precisar ser copiada, aumentando a CI • Em B e C, não pode haver problemas em executar a sub quando o desvio não é tomado sub $4,$5,$6 delay slot delay slot add $1,$2,$3 if $1=0 then sub $4,$5,$6 delay slot CS252-s06, Lec 02-intro

  31. Delayed Branch • Compiler effectiveness for single branch delay slot: • Fills about 60% of branch delay slots • About 80% of instructions executed in branch delay slots useful in computation • About 50% (60% x 80%) of slots usefully filled • Delayed Branch downside: As processor go to deeper pipelines and multiple issue, the branch delay grows and need more than one delay slot • Delayed branching has lost popularity compared to more expensive but more flexible dynamic approaches • Growth in available transistors has made dynamic approaches relatively cheaper CS252-s06, Lec 02-intro

  32. Evaluating Branch Alternatives Assume 4% unconditional branch, 6% conditional branch- untaken, 10% conditional branch-taken Scheduling Branch CPI speedup v. speedup v. scheme penalty unpipelined stall Stall pipeline 3 1.60 3.1 1.0 Predict taken 1 1.20 4.2 1.33 Predict not taken 1 1.14 4.4 1.40 Delayed branch 0.5 1.10 4.5 1.45 CS252-s06, Lec 02-intro

  33. Problems with Pipelining • Exception: An unusual event happens to an instruction during its execution • Examples: divide by zero, undefined opcode • Interrupt: Hardware signal to switch the processor to a new instruction stream • Example: a sound card interrupts when it needs more audio output samples (an audio “click” happens if it is left waiting) • Problem: It must appear that the exception or interrupt must appear between 2 instructions (Ii and Ii+1) • The effect of all instructions up to and including Ii is totalling complete • No effect of any instruction after Ii can take place • The interrupt (exception) handler either aborts program or restarts at instruction Ii+1 CS252-s06, Lec 02-intro

  34. Precise Exceptions in Static Pipelines Key observation: architected state only change in memory and register write stages.

  35. Outra alternativa para reduzir o impacto dos desvios condicionais • Predição de desvios! • Mas, para compreender como implementar, precisamos saber como funcionam os caches! CS252-s06, Lec 02-intro

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