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《EDA 技术与 PLD 设计 》

《EDA 技术与 PLD 设计 》. 第 5 章 VHDL 设计进阶（一） 通信工程学院 尹廷辉讲师 二  五年三月十六日. 用 VHDL 描述触发器. 触发器的功能分类 RS 、 D 、 JK 、 T 和翻转触发器五种 触发器的结构分类 同步、边沿、主从、维持阻塞. library ieee; use ieee.std_logic_1164.all; entity mux2to1 is port(a,b:in std_logic; sel:in std_logic; y:out std_logic);

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《EDA 技术与 PLD 设计 》

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  1. 《EDA技术与PLD设计》 第5章 VHDL设计进阶（一） 通信工程学院 尹廷辉讲师 二五年三月十六日

  2. 用VHDL描述触发器 • 触发器的功能分类 • RS、D、JK、T和翻转触发器五种 • 触发器的结构分类 • 同步、边沿、主从、维持阻塞

  3. library ieee; use ieee.std_logic_1164.all; entity mux2to1 is port(a,b:in std_logic; sel:in std_logic; y:out std_logic); end mux2to1; architecture one of mux2to1 is begin process(a,b,sel) begin if sel='1' then y<=a; else y<=b; end if; end process; end one; 2选1的数据选择器

  4. library ieee; use ieee.std_logic_1164.all; entity mux2to1 is port(a,b:in std_logic; sel:in std_logic; y:out std_logic); end mux2to1; architecture one of mux2to1 is begin process(a,b,sel) begin if sel='1' then y<=a; else end if; end process; end one; 锁存器（同步触发器）高电平触发 当sel=0时，输出保持不变。隐含着存储器。

  5. library ieee; use ieee.std_logic_1164.all; entity latch is port(d:in std_logic; clk:in std_logic; q:out std_logic); end latch; architecture one of latch is begin process(d,clk) begin if clk='0' then q<=d; end if; end process; end one; 锁存器（同步触发器）低电平触发 当sel=1时，输出保持不变。

  6. 两类process语句 • 组合类型的process • 对所有输入信号都敏感 • 例如：process(a,b,sel) • 时序类型的process • 只对时钟或者控制信号敏感 • 例如：process(clk,clr)描述的是锁存器

  7. library ieee; use ieee.std_logic_1164.all; entity dff_a is port ( d : in std_logic; clk : in std_logic; q : out std_logic); end dff_a; architecture behavior OF dff_a is begin process (clk) begin if clk'event and clk = '1' then q <= d; end if; end process; end behavior; 上升沿 clk：信号名称； ‘event :需要信号发生变化。 Clk=‘1’：表示clk变成了高电平。

  8. library ieee; use ieee.std_logic_1164.all; entity dff_a is port ( d : in std_logic; clk : in std_logic; q : out std_logic); end dff_a; architecture behavior OF dff_a is begin process (clk) begin if clk'event and clk = '0' then q <= d; end if; end process; end behavior; 下降沿

  9. library ieee; use ieee.std_logic_1164.all; entity dff_a is port ( d : in std_logic; clk : in std_logic; q : out std_logic); end dff_a; architecture behavior OF dff_a is begin process (clk) begin if rising_edge(clk) then q <= d; end if; end process; end behavior; 上升沿 rising_edge是std_logic_1164的一个函数，表示从0到1的变化。

  10. 思考题：上升沿的JK触发器 • JK触发器的特征方程： library ieee; use ieee.std_logic_1164.all; entity rising_jk is port ( j,k : in std_logic; clk : in std_logic; q : out std_logic); end rising_jk; architecture behavior OF rising_jk is begin process (clk) begin if clk'event and clk='1' then q <= (j and not q) or (not k and q); end if; end process; end behavior;

  11. 带异步复位的D触发器 architecture behavior of dff_clr is begin process(clk, clr) begin if clr = '0' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; end behavior; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dff_clr is port ( clr : std_logic; d, clk : in std_logic; q : out std_logic); end dff_clr;

  12. 带同步复位的D触发器 architecture behavior of dff_clr is begin process(clk) begin if rising_edge(clk) then if clr='0' then q<='0'; else q<=d; end if; end if; end process; end behavior; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dff_clr is port ( clr : std_logic; d, clk : in std_logic; q : out std_logic); end dff_clr;

  13. 思考题：带异步复位/置位的D触发器 • 此种触发器的功能是 （1）当reset=0且set=1时，执行复位功能，输出Q=0； （2）当reset=1且set=0时，执行置位功能，输出Q=1； （3）当reset=1且set=1时，执行D触发器功能，在上升沿到来时，输出Q=D。

  14. 用VHDL描述计数器 • 按时钟性质分 • 同步计数器（如74161） • 异步计数器（如7490） • 按计数方式分 • 二进制计数器 • 非二进制计数器（十进制计数器）

  15. 模8同步计数器 & Z Q0 Q1 1 & 1J 1J 1J C1 C1 C1 Q0 Q1 Q2 1 1K 1K 1K CP 用下降沿JK触发器构成二进制同步计数器的规则： （1）第一个触发器接成J=K=1 （2）其它触发器接成T触发器，Ji=Ki=Qi-1Q0（加法） 或者，Ji=Ki=Qi-1Q0（减法）

  16. 同步模8计数器程序及仿真 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt8 is port(clk:in std_logic; q:buffer std_logic_vector(2 downto 0)); end cnt8; architecture one of cnt8 is begin process(clk) begin if clk'event and clk='0' then q<=q+"001"; end if; end process; end one;

  17. 带使能端en的计数器 & Z Q0 Q1 1 & 1J 1J 1J C1 C1 C1 Q0 Q1 Q2 1 1K 1K 1K EN=1时，计数器计数； EN=0时，计数器保持 & CP EN

  18. 带使能端的模8计数器程序及仿真 architecture one of cnt8 is begin process(clk) begin if en='1' then if clk'event and clk='0' then q<=q+"001"; end if; end if; end process; end one; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt8 is port(clk,en:in std_logic; q:buffer std_logic_vector(2 downto 0)); end cnt8;

  19. 带使能、进位输入端的计数器 & CI Z Q0 Q1 1 & 1J 1J 1J C1 C1 C1 Q0 Q1 Q2 1 1K 1K 1K 当CI=1时，表示有进位输入； 当CI=0时，表示没有进位输入。 & CP EN

  20. 带进位输入和使能端的计数器 process(clk) begin if en='1' then if clk'event and clk='0' then if ci='0' then q<=q+"001"; else q<=q+"001"+"001"; end if; end if; end if; end process; end one; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt8 is port(clk,en,ci:in std_logic; q:buffer std_logic_vector(2 downto 0)); end cnt8; architecture one of cnt8 is begin

  21. 带使能、进位输入、异步复位端 & CI Z Q0 Q1 1 & 1J 1J 1J C1 C1 C1 Q0 Q1 Q2 1 1K 1K 1K 当 =0时，计数器复位到零，异步复位。 & CP EN

  22. process(rst,clk) begin if rst='0' then q<="000"; elsif en='1' then if clk'event and clk='0' then if ci='0' then q<=q+"001"; else q<=q+"001"+"001"; end if; end if; end if; end process; end one; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt8 is port(clk,en,ci,rst:in std_logic; q:buffer std_logic_vector(2 downto 0)); end cnt8; architecture one of cnt8 is begin 如果设计一个同步复位的模8计数器，该如何设计？

  23. 同步复位的模8计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt8 is port(clk,rst:in std_logic; q:buffer std_logic_vector(2 downto 0)); end cnt8; architecture one of cnt8 is begin process(clk) begin if clk'event and clk='0' then if rst='0' then q<="000"; else q<=q+"001"; end if; end if; end process; end one;

  24. 带同步预置的模8计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt8 is port(clk,ld:in std_logic; d:in std_logic_vector(2 downto 0); q:buffer std_logic_vector(2 downto 0)); end cnt8; architecture one of cnt8 is begin process(clk) begin if clk'event and clk='0' then if ld='0' then q<=d; else q<=q+"001"; end if; end if; end process; end one;

  25. 带异步预置的模8计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt8 is port(clk,ld:in std_logic; d:in std_logic_vector(2 downto 0); q:buffer std_logic_vector(2 downto 0)); end cnt8; architecture one of cnt8 is begin process(ld,clk) begin if ld='0' then q<=d; elsif clk'event and clk='0' then q<=q+"001"; end if; end process; end one;

  26. 非二进制计数器举例（模10计数器） architecture one of cnt10 is begin process(clk) begin if clk'event and clk='0' then if q<"1001" then q<=q+"0001"; else q<="0000"; end if; end if; end process; end one; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt10 is port(clk:in std_logic; q:buffer std_logic_vector(3 downto 0)); end cnt10;

  27. 非二进制计数器举例（模100计数器） architecture one of cnt10 is begin process(clk) begin if clk'event and clk='0' then if q<99 then q<=q+1; else q<=0; end if; end if; end process; end one; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt100 is port(clk:in std_logic; q:buffer integer range 0 to 99); end cnt100;

  28. 任意模计数器 • 在《数字电路》课程中，采用反馈复位和反馈预置方法实现任意模计数器。 • 在VHDL中，采用if-else语句实现。 process(clk) begin if clk'event and clk='0' then if q<N-1 then q<=q+1; else q<=0; end if; end if; end process;

  29. 1D 1D 1D 1D C1 C1 C1 C1 寄存器和移位寄存器 Q0 Q1 Q2 Q3 RD CP D0 D1 D2 D3 4边沿D触发器构成的基本寄存器74175

  30. 4位寄存器 library ieee; use ieee.std_logic_1164.all; entity reg4 is port(clk:in std_logic; d:in std_logic_vector(3 downto 0); q:buffer std_logic_vector(3 downto 0)); end reg4; architecture one of reg4 is begin process(clk) begin if clk'event and clk='1' then q<=d; end if; end process; end one;

  31. 4位右移寄存器 architecture one of reg4 is begin process(clk) begin if clk'event and clk='1' then q(0)<=dsr;q(1)<=q(0); q(2)<=q(1);q(3)<=q(2); end if; end process; end one; library ieee; use ieee.std_logic_1164.all; entity reg4 is port(clk,dsr:in std_logic; q:buffer std_logic_vector(0 to 3)); end reg4;

  32. 4位左移寄存器 architecture one of reg4 is begin process(clk) begin if clk'event and clk='1' then q(3)<=dsl;q(2)<=q(3); q(1)<=q(2);q(0)<=q(1); end if; end process; end one; library ieee; use ieee.std_logic_1164.all; entity reg4 is port(clk,dsl:in std_logic; q:buffer std_logic_vector(0 to 3)); end reg4;

  33. 4位双向移位寄存器 process(clk) begin if clk'event and clk='1' then if mode='1' then q(0)<=dsr;q(1)<=q(0); q(2)<=q(1);q(3)<=q(2); else q(3)<=dsl;q(2)<=q(3); q(1)<=q(2);q(0)<=q(1); end if; end if; end process; end one; library ieee; use ieee.std_logic_1164.all; entity reg4 is port(clk,dsr,dsl,mode:in std_logic; q:buffer std_logic_vector(0 to 3)); end reg4; architecture one of reg4 is begin

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