Precision Timed (PRET) Architecture

1. Precision Timed (PRET) Architecture Hiren D. Patel, Ben Lickly, Isaac Liu and Edward A. Lee {hiren,blickly,liuisaac,eal}@eecs.berkeley.edu University of California, Berkeley

2. Most traditional computing abstractions hide timing properties of software Advantages Focus on functionality Push for higher average-case performance Disadvantages Real-time embedded systems Unpredictable Non-repeatable Brittle Timing Properties in Computing Abstractions Programming models and languages Multithreading Compilers, and ISAs Speculative execution, caches, and deep pipelines

3. Resulting Real-time Embedded Systems • Unpredictability • Difficulty in determining timing behavior through analysis • Non-repeatability • Different executions may yield different timing behavior • Brittleness • Small changes have big effects on timing behavior Time as a first class citizen of embedded computing

4. Precision Timed (PRET) Architectures Predictable and repeatable timing Stephen. A. Edwards and Edward. A. Lee, “The case for the Precision Timed (PRET) machine.” In Proceedings of the 44th Annual Conference on Design Automation (San Diego, California, June 04 - 08, 2007). DAC '07. ACM, New York, NY, 264-265.

5. Precision Timed Architecture ISA with timing instructions Round-robin thread scheduling Scratchpad memories Thread-interleaved pipeline Time-triggered arbitration

6. ISA extensions dead [Ip & Edwards in 2006] deadload Deadline instructions Denote the required execution time of a block When decoded Stall instruction until timer value is 0 Then set timer value to new value Timing Instructions: Deadline Block 1 Block 2 Block 3

7. ISA extensions deadbranch deadloadbranch What happens when missing deadlines? Raise exception and perform pre-specified actions Timing Instructions: Exceptions To control timing behaviors in software, we need a predictable underlying architecture

8. Thread-interleaved pipeline: Predictable timing behavior of instructions Pipeline Architecture with Predictable Timing Traditional pipeline: Stall pipeline Dependencies result in complex timing behaviors

9. Thread-interleaved Pipeline with Timing Instructions Thread stalls Main memory access Deadline instructions Replay mechanism Execute same PC next iteration Decrement deadline timers Stall if deadline instruction If not stalled, increment PC

10. Scratchpad memories Software managed caches thread0 thread2 thread4 Memory Hierarchy with Predictable Timing Each thread has a uniquely defined address space 1 cycle latency Shared data goes through to main memory Predictable timingbehavior during cache accesses 13 cycles latency

11. Memory wheel Time-triggered access Each thread must make and complete access within its window Time-triggered Access to Main Memory 90 cycles until thread0 completes Worst-case bound on access time: 13*6 + 12 = 90 cycles Predictable timing behavior when accessing main memory On time On time On time On time On time thread0 thread1 thread2 thread3 thread4 thread5 thread0

12. Video rendering for a computer game Real-time requirements through deadline instructions Autonomous robot finding moving target Anytime algorithms using timing exceptions Eliminating time-exploiting attacks in cryptosystems Repeatable timing behavior through deadline instructions Examples RSA Encryption (RSAREF 2.0) DSA Encryption from OpenSSL (0.9.8j)

13. Predictable Timing and High Performance Code generation from Giotto, SDF, and PTIDES. Timing analysis Real-time network on-chip Programming models and languages with time semantics PRET Machine Scratchpad memory allocation schemes Thread scheduling and synchronizations Multi-PRET architecture

14. Conclusion • Treat time as a first class property of embedded computing • Predictable and repeatable timing behaviors • PRET cycle-accurate simulator • ISA extensions with timing instructions • Architecture with predictable timing behaviors • Download: http://chess.eecs.berkeley.edu/pret/

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