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Lecture 10: Computer Design Basics: The ALU and the Shifter

Lecture 10: Computer Design Basics: The ALU and the Shifter. Soon Tee Teoh CS 147. The ALU. The Arithmetic/Logic Unit Performs both arithmetic and logic operations The Arithmetic Circuit needs to support the following instructions:. Move A G = A Increment G = A + 1 Add G = A + B

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Lecture 10: Computer Design Basics: The ALU and the Shifter

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  1. Lecture 10:Computer Design Basics:The ALU and the Shifter Soon Tee Teoh CS 147

  2. The ALU • The Arithmetic/Logic Unit • Performs both arithmetic and logic operations • The Arithmetic Circuit needs to support the following instructions: Move A G = A Increment G = A + 1 Add G = A + B Subtract G = A + B’ + 1 Decrement G = A - 1 from table 10-8, pg. 454 from table 10-1, pg. 435

  3. The Arithmetic Circuit Cin Cin n A X n-bit parallel adder n G n B n B input logic Y S0 S1 Function table of B input logic S1 S0 Y 0 0 all 0 0 1 B 1 0 B’ 1 1 all 1 Desired operation Inputs S1 S0 Cin G = A + B 0 1 0 G = A + 1 0 0 1 G = A + B 0 1 0 G = A + B’ + 1 1 0 1 G = A – 1 1 1 0

  4. The Logic Unit • Needs to support the following instructions: S0 4-to-1 MUX S1 AND G = A ^ B OR G = A v B Exclusive OR G = A + B NOT G = A’ A B G from table 10-8, pg. 454 from fig 10-8, pg. 437

  5. Putting Arithmetic and Logic Together Cin A B S0 S1 Cin A B S0 S1 Cout to next bit One Stage of Arithmetic Circuit 0 1 2-to-1 MUX G S A B S0 S1 One Stage of Logic Circuit S2 4-bit G Select becomes [ S2 S1 S0 Cin ]

  6. Load enable n load R0 A Select 10 n n 0 1 2 3 MUX load R1 n n B Select 00 load R2 MB Select 0 1 2 3 MUX 00 n n MUX B 0 1 load R3 n Constant 0 1 2 3 decoder A B Arithmetic/Logic Unit Shifter H Select G Select MUX F 0 1 0010 MUX D 0 1 Data from Memory Destination Select 01 0 0 MF Select MD Select

  7. Need to determine input signals Operation MF Select G Select H Select F = A 0 0000 XX F = A+1 0 0001 XX F = A+B 0 0010 XX F = A+B+1 0 0011 XX F = A+B’ 0 0100 XX F = A+B’+1 0 0101 XX F = A-1 0 0110 XX F = A 0 0111 XX F = A ^ B 0 1X00 XX F = A v B 0 1X01 XX F = A + B 0 1X10 XX F = A’ 0 1X11 XX F = B 1 XXXX 00 F = sr B 1 XXXX 01 F = sl B 1 XXXX 10 From Table 10-4, page 443

  8. Timing • Suppose that the propagation delay for each of the components is as follows • 4-1 MUX: 5 ns • 2-1 MUX: 3 ns • AND gate: 1 ns • Register: 4 ns • 2-4 Decoder: 4 ns • ALU: 15 ns • Shifter: 7 ns • Suppose that the set-up time of the registers is 2ns, and the hold time of the registers is 1 ns. • What is the minimum clock period possible for this machine? • What is the maximum clock frequency this machine can achieve? (Note: Clock frequency = Number of clock cycles per second)

  9. Barrel Shifter • Example: 4-bit barrel shifter, can shift input by 0, 1, 2 or 3 bits. • S0S1 determines how many bits to shift (left). • Use 4 4-to-1 multiplexers. D0 D3 D2 D1 D1 D0 D3 D2 0 1 2 3 0 1 2 3 Y0 Y1 4-bit Barrel Shifter S0 S0 S1 S1 D Y 4 4 D2 D1 D0 D3 D3 D2 D1 D0 0 1 2 3 0 1 2 3 Y2 Y3 S0 S1 S0 S0 S1 S1 From Figure 10-9, page 441

  10. Barrel Shifter • 32-bit barrel shifter: can use 32 32-to-1multiplexers • However, large fan-in undesirable. So, use layers of multiplexers D0 D2 0 1 0 1 Y0 D1 D3 0 1 Example: Use 2 layers of 4 2-to-1 multiplexers for 4-bit barrel shifter 0 1 Y1 D2 D0 0 1 0 1 Y2 D3 D1 0 1 0 1 Y3 S1 S0

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