３ D Integration for SOI Pixel Detector

1. T-Micro ３D Integration for SOI Pixel Detector Makoto Motoyoshi (T-Micro)

2. Contents 1. Motivation Device target 2. Technologies and issues SOI Pixel detector process flow Yield process issues and counter measurements 3. Cost down technique of 3D stacking 4. Summary

3. 1. Motivation Target of our 3D technology Realize High Speed Parallel Processing Pixel Sensor with Memory 32 x 32 pixels 6M/4096(5859)pixel arrays Pixel array(BSI type) (0,3) (0,2) (0,1) (0,0) 1024 pixel data (serial) 5859 parallel data ADC Dec Decoder AD Converter 1024x12 bit data (serial) 5859 parallel data 32 x 32 x 12 (12288k) n Memory Array DSP

4. 1. Motivation Target 3D Technology 108 TSV diameter =TSV pitch x 1/2 107 TSV area ratio - Via last process - Interconnect density 104~105/cm2 - Area penalty ≤1 % - Good manufacturability (high yield, reliability) - Low process temperature - Low cost 106 Number of TSV (cm-2) 105 10% 5% 104 1% 103 20 length 101 15 diameter 100 RC Delay (fs) TSV length, diameter (mm) 10 TSV and μ-bump technology with the pitch less than 5μm 10-1 5 RC Delay 10-2 0 10-3 2 4 6 8 12 0 10 TSV pitch (um) M. Koyanagi et al., IEEE Trans. Electron Devices, VOL.53, NO.11, pp.2799-2808, 2006

5. Stacked SOI Pixel detector Back gate electrode Bond Pad BOX(upper tier) Metal interconnect Bump junction BOX(lower tier) p+ n+ + - + - buried p-well + - + - + - n-- + - Si sensor (high resistivity Substrate) + - Charged Particle

6. Process flow (1) < Lower Tier > < Upper Tier > (a) Start with FD-SOI device wafer M4 M3 M2 MOST M1 Active Si~50 nm BOX:200 nm BOX BOX Si High R-Si MOS Tr Si Si *FD: Fully Depleteｄ µ-bump µ-bump (b) µ-bump forming Si Si High R-Si Si Si Si Upper tier adhesive (c) Chip bonding -face to face infrared alignment -temporary bonding -Adhesive injection -permanent bonding (<200℃) Lower tier Si High R-Si

7. SOI pixel detector Chip (After forming u-bump) In μ-bump 10µm Detector Array Upper tier

8. Selection of Wafer/Chip bonding technology Si Si Si Adhesive SiO2 Metal μ-bump Si Si Si SiO2 fusion bonding Polymer adhesive bonding Metal fusion bonding

9. 1. Motivation Selection of Wafer/Chip bonding technology (2) Si Si Metal bump Cu/Sn bump Si Si Metal eutectic bonding Bumping (Pb/Sn, Au, In)

10. Yield model YieldModel of LSI Y= Y0・Y1(D0, A, α) Y0 :Systematic yield Y1 :The fraction of chip sites without process related effects and circuit sensibility A : Chip Area D0 : Density of defects α : Distribution parameter of defects Defect source - dusts or other particlesin the environment, solution, process chamber in the production equipment - pattern defects due to ununiformity of material - oxide defects caused by process damage - statistical factor etc.

11. Yield model Yn :The fraction of chip sites without process related effects and circuit sensibility A : Chip area D0 : Density of defects Y1=exp (-D0A) F(D) 2D0 D0 F(D) 2 1-exp(-D0A) D0A Y2= 2D0 D0 F(D) 1-exp(-2D0A) 2D0A Y3= 2D0 D0 1 (1+SD0A)1/s S0 Y4= S=1.0 F(D) S=0.1 S: shape parameter 2D0 D0

12. Yield Prediction Y=exp(-D1A) Yield 1 Y= （1+D0A） Initial manufacturing Chip Area

13. 1. Motivation Yield and reliability dusts or particles S/D S/D S/D S/D S/D S/D No failure or reliability problem failure No failure Oxide CVD CMP Via patterning Form metal interconnect S/D S/D S/D S/D S/D S/D

14. 1. Motivation Yield and reliability dusts or particles S/D S/D S/D S/D S/D S/D No failure or reliability problem failure No failure Oxide CVD CMP Via patterning Form metal interconnect S/D S/D S/D S/D S/D S/D We can only detect this failure from electrical testing.

15. 1. Motivation Yield and reliability dusts or particles S/D S/D S/D S/D S/D S/D No failure or reliability problem failure No failure Oxide CVD CMP Via patterning Form metal interconnect S/D S/D S/D S/D S/D S/D In case of bonding wafer/chip on wafer /chip surface with dust, Upper Chip Lower Chip If the bonding method which needs microscopic smoothness and cleanliness, bonding yield will be affected by defect density of dusts and particles. So we have chosen the bump bonding with adhesive injection.

16. 1. Motivation Wafer Bonding Method (Tohoku University/T-micro) Bump size (~μm) >>dust or particle size (≤0.2μm) Si dust Adhesive Si Si Si Si Si Wafer or Chip Alignment Temporary Bonding Adhesive Injection In μ-bumps do not have enough mechanical strength, so the combination use of adhesive is indispensable.

17. SOI pixel detector Chip After Si removal Detector Array /Peripheral Circuits Voids

18. Process flow (2) (d) Bulk-Si removal Si High R-Si Back gate adjust electrode Bond Pad Passivation (e) Pad patterning and passivation High R-Si

19. Void problem Void Void Void Void

20. Mechanism of void formation (1) (a) Simple test device Uniform pressure change Upper tier adhesive Lower tier Bump connection (b) Circuit test device No void in pixel array Peripheral circuit Detector array non-uniform pressure change Uniform pressure change voids Top metal void Top metal Passivation layer Top metal adhesive interlayer Bump connection Si-sub

21. Mechanism of void formation (2) Adhesive flow speed F1 Pumping action> capillary action F2 Void Chip area Chip area Scribe line Injection line F3 F4 Void Chip area Chip area F5 F1, F3, F5 > F2, F4 Pumping action< capillary action F1 Void F2 Chip area Chip area Injection line F3 Void F4 Chip area Chip area F5 Void F1, F3, F5 < F2, F4

22. Mechanism of void formation (3) Adhesive flow rate Chip area F1 High density bump area F2 Void F3 F4 F1, F4 > F2, F3

23. Pixel detector chip after Si removal Optimize - bump layout - differential pressure of adhesive injection - process temperature (control the viscosity of adhesive) - wettability of adhesive Void Void Void (a) before improvement (b) after improvement

24. Two types of pixel detector chip B pattern (5mmx 5mm ) Apattern (5mm x 5mm) upper left corner upper right corner after Si removal left lower corner right lower corner Finished Chip

25. Cross sectional SEM image of pixel array Back gate Metal MOS Tr BOX(UT) M1(UT) UT M2(UT) M3(UT) In bump M4(UT) Adhesive M4 (LT) M3(LT) M2(LT) M1(LT) BOX(LT) LT 5μｍ UT: upper tier LT: lower tier

26. Poor wettability

27. In 2.0μm Ti Al5%Cu

28. In bump vs In/Cu bump 2 x 2 um x 2440 bump daisy chain 10000 1.0 Bump Resistance (Ω) 0. 1 0.01 In/Cu In

29. Summary-Technology selection chart Stacked SOI Pixel Detector Wafer/chip bonding Bumping SiO2 fusion bonding metal fusion bonding metal eutectic bonding Bumping Polymeradhesive bonding Manufacturability Cu/Sn Pb/Sn Au In In Cu Low process temp.150~200℃ Combining Adhesive injection Overcome weak mechanical strength Void Chip shift Process issues

30. Prototype of 8” Self-Assembled Chip Bonder

31. Self-Assembly Process with 8-inch Wafer Simultaneously picked-up 500 chips (5mm×5mm) Multi-chip pick-up plate KGD Liquid 180mm KGDs KGDs Alignment accuracy: ~ 400 nm Self-assembled KGDs Hydrophilic bonding area Chip release Self-assembly Liquid on hydrophilic area formed on the wafer 150mm A large number of self-assembled chips 50mm Liquid array on an 8-inch wafer

32. 200 mm 図４　試作製造装置で多数のチップを仮接着したウェーハの全体写真

33. Conclusion • 3D LSI Integration technology using minimum 5μm pitch bump • is verified using SOI stacked pixel detector as circuit level test • device. • In this technology, adhesive injection is found the key technology. Optimizing layout, process parameter and adhesive injection method, this process have completed without void. • The dispersion of bump resistance is still high, the following optimization are still ongoing. • Improvement of wettability between bump and pad • Introducing the new Cu/In IMC bonding • In further development of wafer /chip bonding with few μm pitch bump , it might be necessary to optimize the gap between tiers and volume of bump metal.