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FPGA Fabric Architecture: Concepts and Elements for Logic, Interconnect, and I/O

This article explores the key concepts and elements of FPGA fabric architecture, including logic blocks, interconnects, and I/O pins. It covers topics such as logic synthesis, placement, routing, programming technologies, and reconfiguration. Additionally, it addresses important questions related to area budget, logic elements, interconnects, and I/O blocks in FPGA design.

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FPGA Fabric Architecture: Concepts and Elements for Logic, Interconnect, and I/O

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  1. Topics • FPGA fabric architecture concepts.

  2. Elements of an FPGA fabric • Logic. • Interconnect. • I/O pins. … … IOB IOB IOB LE LE LE interconnect LE LE LE LE LE LE

  3. Terminology • Configuration: bits that determine logic function + interconnect. • CLB: combinational logic block = logic element (LE). • LUT: Lookup table = SRAM used for truth table. • I/O block (IOB): I/O pin + associated logic and electronics.

  4. Logic element • Programmable: • Input connections. • Internal function. • Coarser-grained than logic gates. • Typically 4 inputs. • Generally includes register. • May provide specialized logic. • Adder carry chain.

  5. 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 Example logic element • Lookup table: memory a out b

  6. Logic synthesis • How do we break the function into logic elements? • How do we implement an operation within a logic element?

  7. Placement • Where do we put each piece of logic in the array of logic elements? … LE LE LE LE LE LE LE LE LE

  8. Programmable wiring • Organized into channels. • Many wires per channel. • Connections between wires made at programmable interconnection points. • Must choose: • Channels from source to destination. • Wires within the channels.

  9. Programmable interconnection point D Q

  10. Programmable wiring paths

  11. Choosing a path LE LE

  12. Routing problems • Global routing: • Which combination of channels? • Local routing: • Which wire in each channel? • Routing metrics: • Net length. • Delay.

  13. Segmented wiring Length 1 Length 2

  14. Offset segments

  15. I/O • Fundamental selection: input, output, three-state? • Additional features: • Register. • Voltage levels. • Slew rate.

  16. Programming technologies • SRAM. • Can be programmed many times. • Must be programmed at power-up. • Antifuse. • Programmed once. • Flash. • Similar to SRAM but using flash memory.

  17. Configuration • Must set control bits for: • LE. • Interconnect. • I/O blocks. • Usually configured off-line. • Separate burn-in step (antifuse). • At power-up (SRAM).

  18. FPGA configuration: Bits stay at the device they program. A configuration bit controls a switch or a logic bit. CPU programming: Instructions are fetched from a memory. Instructions select complex operations. Configuration vs. programming memory CPU add r1, r2 IR add r1, r2

  19. Reconfiguration • Some FPGAs are designed for fast configuration. • A few clock cycles, not thousands of clock cycles. • Allows hardware to be changed on-the-fly.

  20. FPGA fabric architecture questions • Given limited area budget: • How many logic elements? • How much interconnect? • How many I/O blocks?

  21. Logic element questions • How many inputs? • How many functions? • All functions of n inputs or eliminate some combinations? • What inputs go to what pieces of the function? • Any specialized logic? • Adder, etc. • What register features?

  22. Interconnect questions • How many wires in each channel? • Uniform distribution of wiring? • How should wires be segmented? • How rich is interconnect between channels? • How long is the average wire? • How much buffering do we add to wires?

  23. I/O block questions • How many pins? • Maximum number of pins determined by package type. • Are pins programmed individually or in groups? • Can all pins perform all functions? • How many logic families do we support?

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