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Multiplication

Multiplication. Lecture L6.2 VHDL Multiply Operator (*). Multiplication. 1101 x 1011 1101 1101 100111 0000 100111 1101 10001111. 13 x11 13 13 143 = 8Fh. Multiplication. 1101 x 1011 1101 1101 100111 0000 100111 1101 10001111.

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Multiplication

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  1. Multiplication Lecture L6.2 VHDL Multiply Operator (*)

  2. Multiplication 1101 x1011 1101 1101 100111 0000 100111 1101 10001111 13 x11 13 13 143 = 8Fh

  3. Multiplication 1101 x1011 1101 1101 100111 0000 100111 1101 10001111 1101 00001011 01101101 adsh 1101 10011110 adsh 1001111 sh 1101 10001111 adsh

  4. std_logic_arith.vhd library IEEE;use IEEE.std_logic_1164.all; package std_logic_arith is type UNSIGNED isarray (NATURALrange <>) of STD_LOGIC; type SIGNED isarray (NATURALrange <>) of STD_LOGIC; subtype SMALL_INT isINTEGERrange 0 to 1; function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; function "*"(L: SIGNED; R: SIGNED) return SIGNED; function "*"(L: SIGNED; R: UNSIGNED) return SIGNED; function "*"(L: UNSIGNED; R: SIGNED) return SIGNED; function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR; function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;

  5. function mult(A,B: UNSIGNED) return UNSIGNED is constant msb: integer:=A'length+B'length-1; variable BA: UNSIGNED(msb downto 0); variable PA: UNSIGNED(msb downto 0); begin if (A(A'left) = 'X' or B(B'left) = 'X') then PA := (others => 'X'); return(PA); endif; PA := (others => '0'); BA := CONV_UNSIGNED(B,(A'length+B'length)); for i in 0 to A'length-1 loop if A(i) = '1' then PA := PA+BA; end if; for j in msb downto 1 loop BA(j):=BA(j-1); end loop; BA(0) := '0'; end loop; return(PA); end; 1101 x1011 1101 1101 100111 0000 100111 1101 10001111

  6. function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is begin return mult(CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)); end;

  7. std_logic_unsigned.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package STD_LOGIC_UNSIGNED is function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;

  8. std_logic_unsigned.vhd (cont.) library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package body STD_LOGIC_UNSIGNED is function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is constant length: INTEGER := maximum(L'length, R'length); variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0); begin result := UNSIGNED(L) * UNSIGNED(R); return std_logic_vector(result); end;

  9. Testing the * operator Use BTN4 to load SW into Ra and Rb and then display product in Rp Control signals: aload bload pload dmsel m2sel(1:0)

  10. Three consecutive pushings of BTN4 Control signals: aload bload pload dmsel m2sel(1:0)

  11. VHDLCanonical Sequential Network init Combinational Network s(t+1) s(t) State Register next state present state x(t) present input process(clk, init) present output clk z(t) process(present_state, x)

  12. -- Title: Mult Control Unit library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity mult_control is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; BTN4: in STD_LOGIC; m2sel: out STD_LOGIC_VECTOR (1 downto 0); aload, bload, dmsel: out STD_LOGIC; pload: out STD_LOGIC ); end mult_control;

  13. mult_control.vhd architecture mult_control_arch of mult_control is type state_type is (sA, sB, sC, sD, sE, sF); signal current_state, next_state: state_type; begin C1: process(current_state, BTN4) begin -- Initialize all outputs pload <= '0'; dmsel <= '0'; aload <= '0'; bload <= '0'; m2sel <= "00";

  14. case current_state is when sA => --wait for BTN4 up if BTN4 = '1' then next_state <= sA; m2sel <= "11"; else next_state <= sB; end if; when sB => --wait for BTN4 down if BTN4 = '1' then next_state <= sC; aload <= '1'; -- A <- SW m2sel <= "00"; else next_state <= sB; m2sel <= "11"; end if;

  15. when sC => --wait for BTN4 up if BTN4 = '1' then next_state <= sC; m2sel <= "00"; else next_state <= sD; end if; when sD => --wait for BTN4 down if BTN4 = '1' then next_state <= sE; dmsel <= '1'; bload <= '1'; -- B <- SW m2sel <= "01"; else next_state <= sD; m2sel <= "00"; end if;

  16. when sE => --wait for BTN4 up if BTN4 = '1' then next_state <= sE; m2sel <= "01"; else next_state <= sF; end if; when sF => --wait for BTN4 down if BTN4 = '1' then next_state <= sA; pload <= '1'; m2sel <= "11"; else next_state <= sF; m2sel <= "01"; end if; end case; end process C1;

  17. statereg: process(clk, clr) -- the state register begin if clr = '1' then current_state <= sA; elsif (clk'event and clk = '1') then current_state <= next_state; end if; end process statereg; end mult_control_arch;

  18. -- Title: Multiply Test library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; use work.mult_components.all; entity mult is port( mclk : in STD_LOGIC; bn : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(1 to 8); BTN4: in STD_LOGIC; led: out std_logic; ldg : out STD_LOGIC; LD : out STD_LOGIC_VECTOR(1 to 8); AtoG : out STD_LOGIC_VECTOR(6 downto 0); A : out STD_LOGIC_VECTOR(3 downto 0) ); end mult; mult.vhd

  19. architecture mult_arch of mult is signal r, p, pout, x, b16, a16: std_logic_vector(15 downto 0); signal as, bs, ain, bin: std_logic_vector(7 downto 0); signal clr, clk, cclk, bnbuf: std_logic; signal clkdiv: std_logic_vector(26 downto 0); signal aload, bload, pload, dmsel: STD_LOGIC; signal m2sel: STD_LOGIC_VECTOR (1 downto 0); constant bus_width8: positive := 8; constant bus_width16: positive := 16;

  20. begin U00: IBUFG port map (I => bn, O => bnbuf); led <= bnbuf; ldg <= '1'; -- enable 74HC373 latch clr <= bnbuf; -- Divide the master clock (50Mhz) process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; clk <= clkdiv(0); -- 25 MHz cclk <= clkdiv(17); -- 190 Hz

  21. a16 <= "00000000" & as; b16 <= "00000000" & bs; p <= as * bs; U1: dmux2g generic map(width => bus_width8) port map (y => SW, a => ain, b => bin, sel => dmsel); U2a: reg generic map(width => bus_width8) port map (d => ain, load => aload, clr => clr, clk =>clk, q => as); U3b: reg generic map(width => bus_width8) port map (d => bin, load => bload, clr => clr, clk =>clk, q => bs); U4p: reg generic map(width => bus_width16) port map (d => p, load => pload, clr => clr, clk =>clk, q => pout);

  22. U5: mux4g generic map(width => bus_width16) port map (a => a16, b => b16, c => pout, d => pout, sel => m2sel, y => r); U6: binbcd port map (B => r, P => x); U7: x7seg port map (x => x, cclk => cclk, clr => clr, AtoG => AtoG, A => A); U8: mult_control port map (clr => clr, clk => clk, BTN4 => BTN4, m2sel => m2sel, aload => aload, bload => bload, dmsel => dmsel, pload => pload); LD <= SW; end mult_arch;

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