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Queueing Theory Modeling of a CPU-GPU System

Queueing Theory Modeling of a CPU-GPU System. September 15, 2010. Lindsay B. H. May, Ph.D. Systems Engineer. Problem/Goals. GPGPUs have been touted as the solution to the loss of the Altivec engine in PowerPCs in the embedded space We set out to answer a few questions…

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Queueing Theory Modeling of a CPU-GPU System

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  1. Queueing Theory Modeling of a CPU-GPU System September 15, 2010 Lindsay B. H. May, Ph.D. Systems Engineer

  2. Problem/Goals • GPGPUs have been touted as the solution to the loss of the Altivec engine in PowerPCs in the embedded space • We set out to answer a few questions… • Are GPGPUs all that they are purported to be? • What are some of the defining architectural limitations? • We know they’re good for graphics but how well do they map into our problem space? • Is there a discernable task/data level parallelism “line” defined by the architecture? • Is there a reasonable mathematical modeling approach to this problem?

  3. SM3 SM2 SM net2 M0 M0 M0 M0 P01 P0M OpenCL Model, Kuck Diagram, and Queueing Model CPU Global Memory PCIe Connection Compute Device Memory Compute Device GPU Global Memory Station 1 Global/Constant Memory Data Cache Local Memory Local Memory SM net3 Compute Unit 1 Compute Unit N Work Item 1 Work Item M Work Item 1 Work Item M GPU Shared Memory SM1 SM1 Private Memory Private Memory Private Memory Private Memory SM net1 SM net1 Station 2 Station 3 P01 P0M Depends on shader clock rate Compute Units

  4. M0 P0 Queueing Equations M/M/1/K Arrival Rate (l) Queue size = Kq K = Kq+1 r*, l* include effects of blocking Server GPGPUs for HPEC – Hype or Hope? Service Rate (m)

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